Patrick Edward Ross

US Patent:

RE38134, Jun 3, 2003

Filed:

Oct 3, 2000

Appl. No.:

09/679447

Inventors:

Patrick Delaney Ross - Sunnyvale CA
Bradley David Strand - Los Gatos CA
Dave Olson - Palo Alto CA
Sanjay Singal - Mountain View CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 1314

US Classification:

710 20, 710 21, 710 29, 710 32, 710 36, 710 40, 710117, 370232, 370235, 709235

Abstract:

The present invention comprises a method and system for implementing prioritized communications in a computer system. The present invention is implemented on a computer system having a microprocessor and a plurality of peripheral devices coupled to the computer system. The system of the present invention determines a first priority level and determines a second priority level. The system of the present invention receives a bandwidth allocation request from a software process to transfer data at the first priority level between two or more peripheral devices. The system subsequently allocates a first priority data transfer bandwidth between the devices in response to the request and performs a first data transfer between the devices using the first priority data transfer bandwidth. In addition, the system of the present invention performs a second data transfer between other devices using a second priority data transfer bandwidth. The second data transfer occurs at a second priority level.

US Patent:

7020720, Mar 28, 2006

Filed:

Nov 27, 2001

Appl. No.:

09/996277

Inventors:

David B. Donahue - Mountain View CA, US
Benn Bollay - San Francisco CA, US
Patrick Ross - Sunnyvale CA, US

Assignee:

The DirecTV Group, Inc. - El Segundo CA

International Classification:

G06F 15/16

US Classification:

709245

Abstract:

A first publically routable IP address and a second publically routable IP address (bypass IP address) is firstly received from an Internet Service Provider (ISP) that forms part of a public network. An instruction to assign the second publically routable IP address to the host computer is then received. The first publically routable IP address is assigned to a Network Address Translation (NAT) service on the gateway and the second publically routable IP address is allocated to the host computer. Finally, the second publically routable IP address is allocated to the host computer. This allows the host computer to be configured to enable it to receive unsolicited packets from the public network through the gateway. A gateway and computer program product are also provided.

US Patent:

20100036900, Feb 11, 2010

Filed:

Jul 31, 2009

Appl. No.:

12/533179

Inventors:

Patrick D. Ross - Sunnyvale CA, US

International Classification:

G06F 7/58
G06F 1/02

US Classification:

708254, 708270

Abstract:

A system and method of generating a one-way function and thereby producing a random-value stream. Steps include: providing a plurality of memory cells addressed according to a domain value wherein any given domain value maps to all possible range values; generating a random domain value associated with one of the memory cells; reading a data value associated with the generated random domain value; generating dynamically enhanced data by providing an additional quantity of data; removing suspected non-random portions thereby creating source data; validating the source data according to a minimum randomness requirement, thereby creating a validated source data; and integrating the validated source data with the memory cell locations using a random edit process that is a masking, a displacement-in-time, a chaos engine, an XOR, an overwrite, an expand, a remove, a control plane, or an address plane module. The expand module inserts a noise chunk.

US Patent:

20110029588, Feb 3, 2011

Filed:

Oct 16, 2009

Appl. No.:

12/580965

Inventors:

Patrick D. Ross - Sunnyvale CA, US

International Classification:

G06F 7/58

US Classification:

708254, 708250

Abstract:

A system and method of generating a one-way function and thereby producing a random-value stream. Steps include: providing a plurality of memory cells addressed according to a domain value wherein any given domain value maps to all possible range values; generating a random domain value associated with one of the memory cells; reading a data value associated with the generated random domain value; generating dynamically enhanced data by providing an additional quantity of data; removing suspected non-random portions thereby creating source data; validating the source data according to a minimum randomness requirement, thereby creating a validated source data; and integrating the validated source data with the memory cell locations using a random edit process that is a masking, a displacement-in-time, a chaos engine, an XOR, an overwrite, an expand, a remove, a control plane, or an address plane module. The expand module inserts a noise chunk.

US Patent:

20120303924, Nov 29, 2012

Filed:

May 29, 2012

Appl. No.:

13/482723

Inventors:

Patrick D. Ross - Sunnyvale CA, US

International Classification:

G06F 12/00

US Classification:

711170

Abstract:

A system, method, and device for stochastically processing data. There is an architect module operating on a processor configured to manage and control stochastic processing of data, a non-deterministic data pool module configured to provide a stream of non-deterministic values that are not derived from a function, a plurality of functionally equivalent data processing modules each configured to stochastically process data as called upon by the architect module, a data feed configured to feed a data set desired to be stochastically processed, and a structure memory module including a memory storage device and configured to provide sufficient information for the architect module to duplicate a predefined processing architecture and to record a utilized processing architecture.

US Patent:

56806248, Oct 21, 1997

Filed:

Dec 21, 1993

Appl. No.:

8/171723

Inventors:

Patrick Delaney Ross - Sunnyvale CA

Assignee:

Object Licensing Corporation - Cupertino CA

International Classification:

G06F 940

US Classification:

395734

Abstract:

A method and apparatus for an innovative, object-oriented hardware independent interface to the external world. The interrupt services are part of an overall IO model providing an object base IO system that supports dynamic configuration of the system. Object processing is architected into even the lowest lever routines in the preferred embodiment of the invention. This includes an object oriented design all the way down to interrupt processing abstractions. These interrupt abstractions provide an architecturally sound framework for the dynamic installation, configuration, and timely execution of interrupt handlers.

US Patent:

53718844, Dec 6, 1994

Filed:

Dec 21, 1993

Appl. No.:

8/171600

Inventors:

Patrick D. Ross - Sunnyvale CA

Assignee:

Taligent, Inc. - Cupertino CA

International Classification:

G06F 1100

US Classification:

395575

Abstract:

A method and apparatus for an innovative, object-oriented hardware independent interface to the external world. The interrupt services are part of an overall IO model providing an object base IO system that supports dynamic configuration of the system. Object processing is architected into even the lowest lever routines in the preferred embodiment of the invention. This includes an object oriented design all the way down to interrupt processing abstractions. These interrupt abstractions provide an architecturally sound framework for the dynamic installation, configuration, and timely execution of interrupt handlers.

US Patent:

45368376, Aug 20, 1985

Filed:

May 25, 1982

Appl. No.:

6/381991

Inventors:

Robert A. Olson - Los Altos CA
Patrick D. Ross - Sunnyvale CA

Assignee:

Elxsi - San Jose CA

International Classification:

G06F 700
G06F 1304

US Classification:

364200

Abstract:

A disk file management system for use in a data processing system that includes at least one disk drive. The disk space is organized on the basis of logical cylinders, with each logical cylinder including a plurality of disk pages and a cylinder control block ("CCB"). Each entry in the CCB corresponds to a page in the CCB's cylinder. Depending on whether a page is allocated to a file or not, the corresponding CCB entry is a file map entry for a file to which the page is allocated or an entry in a free space map. For a given file, each file map entry includes up to two pointers so that the totality of page map entries for the file defines an unbalanced binary tree structure that consists of a sequence of balanced binary trees of increasing size. The free space map for a given cylinder is preferably a chained free space list.