Patrick J Sheridan

US Patent:

20230101310, Mar 30, 2023

Filed:

Jul 14, 2022

Appl. No.:

17/865102

Inventors:

- Boise ID, US
Patrick Michael Sheridan - Boulder CO, US

International Classification:

G11C 7/10

Abstract:

Disclosed in some examples are methods, systems, memory devices, and machine-readable mediums which store a single compressed value per line with a marker value in a front of the compressed version of the memory line. In some examples, the only value stored in the memory line is the value normally stored therein. This removes the complexity of the prediction tables and the inclusion of invalid values as well as preventing the penalty when those prediction tables are wrong. Furthermore, by inclusion of the marker in the beginning of the memory line, the system can quickly determine the compression status of the memory line without having to read the entire line. That is, it can quickly stop reading the rest of the memory line once the compressed data is read out which saves the memory device from having to read the entire line.

US Patent:

20210073139, Mar 11, 2021

Filed:

Sep 6, 2019

Appl. No.:

16/563628

Inventors:

- Boise ID, US
Patrick Michael Sheridan - Boulder CO, US

International Classification:

G06F 12/1009
G06F 12/06

Abstract:

A method for managing logical-to-physical (L2P) mappings in a memory subsystem is described. The method includes updating, by a set of processing units, an L2P table based on a set of journal pages from the non-volatile memory. The L2P table prior to the update includes a first set of entries from a table snapshot and the table includes a second set of entries following the update from a set of journal pages. Each L2P table entry (1) corresponds to a logical address in a set of logical addresses and (2) includes a physical address of a set of memory components. The set of logical addresses are categorized into zones and each processing unit is assigned to a separate zone such that each processing unit updates the first set of entries based on an assigned zone of a corresponding logical address and each zone includes at least two non-contiguous logical addresses.