Patrick Stephen Thomas

US Patent:

7247570, Jul 24, 2007

Filed:

Aug 19, 2004

Appl. No.:

10/922583

Inventors:

Patrick Thomas - Meridian ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/311

US Classification:

438700, 257E21532

Abstract:

In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars, and active areas in a substrate. Preferably, two substrate etch processes use the masks to form three levels of bulk silicon.

US Patent:

7413480, Aug 19, 2008

Filed:

Jul 27, 2006

Appl. No.:

11/494420

Inventors:

Patrick Thomas - Meridian ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/311

US Classification:

439700, 257E21532

Abstract:

In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars, and active areas in a substrate. Preferably, two substrate etch processes use the masks to form three levels of bulk silicon.

US Patent:

7723756, May 25, 2010

Filed:

Mar 7, 2007

Appl. No.:

11/683122

Inventors:

Patrick Thomas - Meridian ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 29/76
H01L 29/00

US Classification:

257213, 257510, 257E29242, 257E29255

Abstract:

In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars, and active areas in a substrate. Preferably, two substrate etch processes use the masks to form three levels of bulk silicon.

US Patent:

8026579, Sep 27, 2011

Filed:

May 19, 2010

Appl. No.:

12/783462

Inventors:

Patrick Thomas - Meridian ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 39/00

US Classification:

257662, 257E29026

Abstract:

In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars, and active areas in a substrate. Preferably, two substrate etch processes use the masks to form three levels of bulk silicon.

US Patent:

8330246, Dec 11, 2012

Filed:

Sep 7, 2011

Appl. No.:

13/227187

Inventors:

Patrick Thomas - Meridian ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 29/00
H01L 29/06

US Classification:

257510, 257622, 257E29026

Abstract:

In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars, and active areas in a substrate. Preferably, two substrate etch processes use the masks to form three levels of bulk silicon.

US Patent:

8629533, Jan 14, 2014

Filed:

Nov 6, 2012

Appl. No.:

13/670209

Inventors:

Patrick Thomas - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 29/00
H01L 29/06

US Classification:

257622, 257510, 257E29026

Abstract:

In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars, and active areas in a substrate. Preferably, two substrate etch processes use the masks to form three levels of bulk silicon.

US Patent:

20220281330, Sep 8, 2022

Filed:

Nov 5, 2021

Appl. No.:

17/453806

Inventors:

Patrick Allan Thomas - Yorba Linda CA, US

International Classification:

B60L 53/16
B60R 16/02
H01R 13/717
H01R 24/68
B60L 53/66

Abstract:

A power inlet device and system for use with large vehicles comprising a power connection port; a wireless communication module; a monitoring module; and one or more indicator lights; wherein the monitoring module monitors for error conditions; wherein the error conditions comprise ground not connected, neutral not connected, and reverse polarity; wherein the one or more indicator lights comprise a general status indicator and one or more specific status indicators; wherein the one or more specific status indicators comprise a ground indicator, neutral indicator, and reverse polarity indicator; wherein the one or more specific status indicators are configured to ignite when the monitoring module detects an error condition; wherein the general status indicator is configured to ignite when the monitoring module detects an error condition.

US Patent:

20210273447, Sep 2, 2021

Filed:

May 20, 2021

Appl. No.:

17/326190

Inventors:

- Anaheim CA, US
Patrick Allan Thomas - Yorba Linda CA, US

International Classification:

H02H 9/04
B60P 3/36
B60R 16/03
H02H 1/00

Abstract:

A recreational vehicle power monitoring and reporting device. The device includes a power input connection, a power output connection, a power conditioner module, and a power monitoring module. The power conditioner module includes a surge protector and the power monitoring module includes on or more sensors. The power condition module is removeable, replaceable, and independent of the power monitoring module.