Patrick O Weber

US Patent:

6495083, Dec 17, 2002

Filed:

May 17, 1999

Appl. No.:

09/312705

Inventors:

Patrick O. Weber - San Jose CA

Assignee:

Hestia Technologies, Inc. - Santa Clara CA

International Classification:

B29C 4502

US Classification:

26427215, 26427217, 29841, 425116, 425812

Abstract:

An integrated circuit chip package according to the present invention includes an integrated circuit chip mounted on a substrate by a plurality of solder bumps. A mold compound is used for underfilling air gaps between the chip and the substrate. The integrated circuit chip package is formed by placing the chip and substrate within a mold cavity and pressing a transfer mold compound into the mold cavity. Air spaces between the integrated circuit chip and the substrate are underfilled by the mold compound as it is pressed in between the integrated circuit chip and the substrate. Air is allowed to escape from between the chip and the substrate during the underfilling through a vent which extends through the substrate. The underfilling material may also be used to encapsulate the chip at the same time that underfilling is performed.

US Patent:

6560122, May 6, 2003

Filed:

Sep 28, 2001

Appl. No.:

09/967676

Inventors:

Patrick O. Weber - Mountain View CA

Assignee:

Hestia Technologies, Inc. - Santa Clara CA

International Classification:

H01L 2331

US Classification:

361783, 361760, 361770, 257667, 257737, 257738, 257778, 257787, 257789, 174260

Abstract:

An integrated circuit chip package according to the present invention includes an integrated circuit chip that is mounted on a substrate by a reflow process and by a plurality of solder bumps. At least one standoff is located between the circuit chip and the substrate to maintain a distance between the circuit chip and the substrate during the reflow process. A mold compound is used for underfilling air gaps between the chip and the substrate. The integrated circuit chip package is formed by placing the chip and substrate within a mold cavity and pressing a transfer mold compound into the mold cavity. Air spaces between the integrated circuit chip and the substrate are underfilled by the mold compound as it is pressed in between the integrated circuit chip, the standoffs and the substrate. Air is allowed to escape from between the chip and the substrate during the underfilling through a vent which extends through the substrate. The underfilling material may also be used to encapsulate the chip at the same time that underfilling is performed.

US Patent:

6667439, Dec 23, 2003

Filed:

Aug 16, 2001

Appl. No.:

09/931378

Inventors:

Matthew M. Salatino - Satellite Beach FL
Patrick O. Weber - Mountain View CA

Assignee:

Authentec, Inc. - Melbourne FL
Hestia Technologies, Inc. - Santa Clara CA

International Classification:

H01L 2300

US Classification:

174 521, 361728, 361752, 257690, 257787

Abstract:

An IC package preferably includes an IC and encapsulating material surrounding the IC, with the encapsulating material having an opening therein to define an exposed portion of the IC. Vestigial portions of encapsulating material may be left on the exposed portion of the IC and spaced inwardly from a periphery of the opening based upon molding using a mold protrusion which includes a bleed-through retention channel positioned inwardly from peripheral edges. The channel collects and retains any bleed-through of the encapsulating material. The IC package may further include a leadframe carrying the IC. The leadframe may include a die pad, finger portions, and a plurality of die pad support bars. The die pad may be downset below a level of the finger portions. Each of the die pad support bars may be resiliently deformed to accommodate the downset of the die pad.

US Patent:

7049166, May 23, 2006

Filed:

Aug 16, 2001

Appl. No.:

09/931587

Inventors:

Matthew M. Salatino - Satellite Beach FL, US
Patrick O. Weber - Mountain View CA, US

Assignee:

Authentec, Inc. - Melbourne FL
Hestia Technologies, Inc. - Santa Clara CA

International Classification:

H01L 21/00
H01L 21/44
H01L 21/48
H01L 21/50

US Classification:

438 64, 438115, 438116, 438117, 438118, 438123, 438124, 438127, 26427215

Abstract:

A method for making an IC package preferably includes providing a mold including first and second mold portions, and wherein the first mold portion carries a mold protrusion defining an IC-contact surface with peripheral edges and a bleed-through retention channel positioned inwardly from the peripheral edges. The method also preferably includes closing the first and second mold portions around the IC and injecting encapsulating material into the mold to encapsulate the IC and make the IC package having an exposed portion of the IC adjacent the mold protrusion. Morever, the bleed-through retention channel retains any encapsulating material bleeding beneath the peripheral edges of the IC contact surface, and prevents the encapsulating material from reaching further onto the exposed portion of the IC. The method may also include releasing the IC package with the exposed portion from the mold.

US Patent:

20100014234, Jan 21, 2010

Filed:

Jul 16, 2008

Appl. No.:

12/174518

Inventors:

Patrick O. Weber - Santa Clara CA, US

Assignee:

HESTIA TECHNOLOGIES, INC. - Santa Clara CA

International Classification:

H05K 7/18
B29D 11/00
H05K 3/20

US Classification:

36167906, 264 17, 29831

Abstract:

A method of manufacturing a display monitor, the method comprising: molding a pixel array frame having a plurality of pixel cavities and at least one pixel wall positioned adjacent to at least two pixel cavities, at least one of the pixel cavities having a light pit therein; molding a light diffusing material in the pixel cavities, wherein the light diffusing material does not enter the light pit; selecting a substrate having a top surface and a bottom surface, the substrate having a light source, such as a LED, on the top surface; coupling the bottom surface of the substrate to a printed circuit board configured to controllably operate the light source, wherein the light source is received within the light pit; and coupling the molded pixel array frame to the substrate.

US Patent:

20110017264, Jan 27, 2011

Filed:

Feb 19, 2009

Appl. No.:

12/389310

Inventors:

Patrick Weber - Santa Clara CA, US
Kevin Gibson - Redwood City CA, US
Ramon Rosal Reglos - San Ramon CA, US
Rick Briere - Santa Clara CA, US
Alelie Funcell - Fremont CA, US

Assignee:

Solaria Corporation - Fremont CA

International Classification:

H01L 31/052

US Classification:

136246

Abstract:

A photovoltaic device. The photovoltaic device includes a photovoltaic region including a surface region and characterized by a first thermal expansion constant. The surface region includes a first portion and a second portion, the second portion includes a first edge region and a second edge region. The photovoltaic device includes a concentrator element comprising substantially of a polymer material and being characterized by a second thermal expansion constant. The concentrator element includes an aperture region and an exit region. The photovoltaic device includes an elastomer material to couple the first portion of the surface region of the photovoltaic region to the exit region of the concentrator element, while the first edge region and the second edge region remain exposed. The first edge region and the second edge region allow for compensation by at least thermal expansion of the concentrator element for a change in temperature ranging from about −45 Degrees Celsius to about 95 Degrees Celsius to maintain the exit region to be optically coupled to the photovoltaic region.

US Patent:

20130058148, Mar 7, 2013

Filed:

Feb 24, 2012

Appl. No.:

13/404995

Inventors:

Allan CANTLE - Westlake Village CA, US
Patrick WEBER - Oxnard CA, US
Mark GILLIAM - Thousand Oaks CA, US
Prashant JOSHI - Thousand Oaks CA, US

International Classification:

G11C 5/06

US Classification:

365 63

Abstract:

Solid state memory modules are disclosed having increased density for module size/footprint. Different embodiments also provide for improved interconnect arrangements between the memory modules and the corresponding field programmable gate array (FPGA), micro-processor (μP), or application-specific integrated circuit (ASIC). These interconnects can provide for greater module interconnect flexibility, operating speed and operating efficiency. Some memory module embodiments according to the present invention comprises a plurality of solid state memory devices arranged on a first printed circuit board. A second printed circuit board is on and electrically connected to the first printed circuit board, with the second printed circuit board having a pin-out for direct coupling to a host device.

US Patent:

60381361, Mar 14, 2000

Filed:

Oct 29, 1997

Appl. No.:

8/959927

Inventors:

Patrick O. Weber - San Jose CA

Assignee:

Hestia Technologies, Inc. - Sunnyvale CA

International Classification:

H01L 2331

US Classification:

361783

Abstract:

An integrated circuit chip package according to the present invention includes an integrated circuit chip mounted on a substrate by a plurality of solder bumps. A mold compound is used for underfilling air gaps between the chip and the substrate. The integrated circuit chip package is formed by placing the chip and substrate within a mold cavity and pressing a transfer mold compound into the mold cavity. Air spaces between the integrated circuit chip and the substrate are underfilled by the mold compound as it is pressed in between the integrated circuit chip and the substrate. Air is allowed to escape from between the chip and the substrate during the underfilling through a vent which extends through the substrate. The underfilling material may also be used to encapsulate the chip at the same time that underfilling is performed.