Paul Raymond Boyer

US Patent:

49026402, Feb 20, 1990

Filed:

Aug 19, 1987

Appl. No.:

7/087176

Inventors:

Jack Sachitano - Portland OR
Hee K. Park - Seoul, KR
Paul K. Boyer - Beaverton OR
Gregory C. Eiden - Madison WI
Tadanori Yamaguchi - Hillsboro OR

Assignee:

Tektronix, Inc. - Beaverton OR

International Classification:

H01L 2170
H01L 2700

US Classification:

437 57

Abstract:

A mixed bipolar-CMOS self-aligned process and integrated circuit provide a high performance NPN bipolar transistor in parallel to fabrication of a PMOSFET and an NMOSFET. Gate and base contacts are formed in a first polysilicon layer. The base contacts are implanted with P+ ion concentrations for diffusing base contact regions of the substrate in a later drive-in step. Source and drain contacts and emitter contacts are formed in a second polysilicon layer. The source and drain contacts are formed as a unit and then separated into discrete contacts by a spin-on polymer planarization and etch-back procedure. Lightly-doped lateral margins of the source, drain and base regions are ion-implanted in an initial low concentration (e. g. about 10. sup. 13 atoms/cm. sup. 2). The gate and base contact structures serve as a mask to self-align the implants.

US Patent:

48267821, May 2, 1989

Filed:

Apr 17, 1987

Appl. No.:

7/040447

Inventors:

Jack Sachitano - Portland OR
Paul K. Boyer - Beaverton OR
Hee K. Park - Seoul, KR
Gregory C. Eiden - Madison WI

Assignee:

Tektronix, Inc. - Beaverton OR

International Classification:

H01L 21265

US Classification:

437 44

Abstract:

An intermediate structure in the fabrication of a metal-oxide semiconductor field-effect transistor is made from a substrate of p+ silicon having an elongate insulated gate structure on its main face. First and second areas of the main face are exposed along first and second opposite sides respectively of the gate structure. Donor impurity atoms are introduced into the substrate by way of at least the first area of the main face, to achieve a predetermined concentration of electrons in a region of the substrate that is subjacent the first area of the main face. The gate structure is opague to the impurity atoms. A sidewall of silicon dioxide is formed along the first side of the gate structure, whereby a strip of the first area of the main face is covered by the sidewall and other parts of the first area remain exposed adjacent the sidewall. Donor impurity atoms to which the gate structure and the sidewall are opaque are introduced into the substrate by way of the portion of the first area that is exposed adjacent the sidewall. A layer of polysilicon is disposite over the portion of the first area of the main face that is exposed adjacent the sidewall.