Paul C Butler

US Patent:

7227918, Jun 5, 2007

Filed:

Mar 13, 2001

Appl. No.:

09/805843

Inventors:

Edward Aung - San Leandro CA, US
Henry Lui - San Jose CA, US
Paul Butler - Mesa AZ, US
John Turner - Santa Cruz CA, US
Rakesh Patel - Cupertino CA, US
Chong Lee - San Ramon CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H04L 7/00

US Classification:

375355

Abstract:

A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.

US Patent:

7333570, Feb 19, 2008

Filed:

Jun 3, 2003

Appl. No.:

10/454731

Inventors:

Edward Aung - San Leandro CA, US
Henry Lui - San Jose CA, US
Paul Butler - Mesa AZ, US
John Turner - Santa Cruz CA, US
Rakesh Patel - Cupertino CA, US
Chong Lee - San Ramon CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H04L 27/00

US Classification:

375326, 375354, 375371

Abstract:

A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.

US Patent:

7684532, Mar 23, 2010

Filed:

Apr 25, 2007

Appl. No.:

11/796136

Inventors:

Edward Aung - San Leandro CA, US
Henry Lui - San Jose CA, US
Paul Butler - Mesa AZ, US
John Turner - Santa Cruz CA, US
Rakesh Patel - Cupertino CA, US
Chong Lee - San Ramon CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H04L 7/00

US Classification:

375355, 375358

Abstract:

A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.

US Patent:

20210320323, Oct 14, 2021

Filed:

Feb 25, 2021

Appl. No.:

17/185122

Inventors:

Aditi CHANDRA - Los Gatos CA, US
Richard VAN DER LINDE - San Jose CA, US
Paul BUTLER - San Jose CA, US
Mao ITO - Santa Cruz CA, US
Jon SIMMONS - San Jose CA, US
Miki TRIFUNOVIC - San Jose CA, US
Alex YAN - San Jose CA, US
Arvind KAMATH - Los Altos CA, US
Shoba RAO - San Jose CA, US

International Classification:

H01M 10/0562
H01M 10/0583
H01M 50/178

Abstract:

A solid-state battery and a method of making the same are disclosed. The battery includes a base frame or support, first and second exterior contacts on the base frame/support, stacked solid-state battery unit cells, first and second electrical connections, and encapsulation in contact with the base frame/support and covering the solid-state battery unit cells and the electrical connections. Each stacked solid-state battery unit cell is on a metal substrate and has exposed cathode and anode current collectors. The electrical connections respectively electrically connect the exposed cathode and anode current collectors to the first and second exterior contacts. The method includes forming the stacked solid-state battery unit cells on the base frame/support, forming the exterior contacts on the base frame/support, electrically connecting the exposed cathode and anode current collectors to the respective exterior contacts, and encapsulating the solid-state battery unit cells and the electrical connections.

US Patent:

20170155529, Jun 1, 2017

Filed:

Dec 12, 2016

Appl. No.:

15/376188

Inventors:

- San Jose CA, US
Henry Lui - San Jose CA, US
Paul Butler - Mesa AZ, US
John Turner - Santa Cruz CA, US
Rakesh Patel - Cupertino CA, US
Chong Lee - San Ramon CA, US

International Classification:

H04L 25/03
H04L 7/033
H04L 25/02

Abstract:

A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.

US Patent:

20170077754, Mar 16, 2017

Filed:

Mar 30, 2016

Appl. No.:

15/085177

Inventors:

- San Diego CA, US
Paul Brandon Butler - San Jose CA, US
Mahbod Mofidi - San Diego CA, US
Francesco Carobolante - San Diego CA, US

International Classification:

H02J 50/12
H04B 5/00
H01F 41/06
H02J 7/02
H01F 38/14

Abstract:

In one aspect, an apparatus for wirelessly coupling with other devices is provided. The apparatus includes a metallic cover having a removed portion. The apparatus comprises a first coil substantially wound around the removed portion of the metallic cover and configured to communicate with at least one other device via a communications protocol. The metallic cover comprises a second coil substantially wound around the removed portion of the metallic cover and configured to wirelessly and inductively receive charging power sufficient to charge or power the apparatus from at least one wireless charging power transmitter.