Paul E Calvert

US Patent:

6628621, Sep 30, 2003

Filed:

Nov 2, 1999

Appl. No.:

09/432707

Inventors:

Robert Scott Appleton - Madison AL
Andrew L. Plankenhorn - Hazel Green AL
Paul E. Calvert - Laceys Spring AL
Steven Creg Killen - Madison AL

Assignee:

Adtran Inc. - Huntsville AL

International Classification:

H04J 116

US Classification:

370249, 370241, 370250, 370251, 714715, 714716, 379 2701, 379 2703, 379 2704, 379 2705

Abstract:

A bit error rate test (BERT) system is configured as a field programmable gate array that emulates multiple independent BERT generators. The BERT generators produce test frames containing test pattern codes associated with respectively different time division multiplexed (TDM) digital communication channels, that are not necessarily mutually contiguous within a plurality of TDM timeslots of a network communication frame serving digital communication circuits. A framing unit assembles the test code patterns into a test frame and transmits the test frame over a serial network interface to a plurality of digital channel units of a channel bank. The framing unit also interfaces contents of test code patterns within test frames returned from the channel units over the serial network interface with a plurality of data channel-specific virtual BERT receivers, associated with respective digital communication channels. A bit error processor determines errors in the contents of the test code patterns within returned test frames.