Paul B Cheng

US Patent:

6362992, Mar 26, 2002

Filed:

Oct 6, 2000

Appl. No.:

09/684589

Inventors:

Paul C. Cheng - San Jose CA

Assignee:

Purple Ray, Inc. - Campbell CA

International Classification:

G11C 1500

US Classification:

365 49, 36518907

Abstract:

A binary-ternary configurable content addressable memory (CAM) ( ). A plurality of CAM cells ( ) including comparator logic cells ( ) and paired storage locations ( ) are directed by a signal at a mode terminal ( ) to compare data provided at an input bus ( ), either in binary mode against pre-stored content data or in ternary mode against pre-stored content and mask data. The comparator logic cells ( ) generate respective bit signals ( ) based on such comparison, and in this manner the plurality of CAM cells ( ) may collectively be part of a CAM array block ( ), which may optionally in turn work with a match detection block ( ) to generate a match signal ( ), and which may optionally in turn work with a priority encoder block ( ) to generate a result signal at a result output ( ).

US Patent:

6629099, Sep 30, 2003

Filed:

Dec 7, 2000

Appl. No.:

09/733231

Inventors:

Paul C. Cheng - San Jose CA

Assignee:

Integrated Silicon Solution, Inc. - Santa Clara CA

International Classification:

G06F 1730

US Classification:

707 10, 707 6, 707 3

Abstract:

A parallel search engine able to receive commands via a search instruction input and data words via a search data input. The commands received, which are optionally programmable, control operation of a data dispatch unit and a result dispatch unit. The data words received are sent by the data dispatch unit as search data to a CAM module array made up of CAM modules interconnected by a cascade information bus for comparison against pre-stored comparand databases. The CAM modules of the CAM module array provide search results to the result dispatch unit which generates results, typically multiple in parallel, at a result output. Optionally, multiple of the parallel search engines may be cascaded by connection to an expansion bus to form a mega search engine.

US Patent:

6704216, Mar 9, 2004

Filed:

Aug 15, 2002

Appl. No.:

10/064770

Inventors:

Paul Cheng - San Jose CA
Nelson L. Chow - Mountain View CA

Assignee:

Integrated Silicon Solution, Inc. - Santa Clara CA

International Classification:

G11C 700

US Classification:

365 49, 365203, 365204, 365202, 36518907, 365 51

Abstract:

A content addressable memory (CAM)( ) and method having a data-in sub-circuit ( ), memory cells ( ), a match-high line ( ), a match-low line ( ), and pre-charge devices ( ). Input lines ( ) from the data-in sub-circuit ( ) are not necessarily discharged to ground in every cycle of a clock signal ( ) used by the memory cells ( ). Further, the pre-charge devices ( ) may be operated at one half of the rate of the clock signal ( ). Yet further, the CAM ( ) may be selectively configured to operate in either binary or ternary mode.

US Patent:

6707505, Mar 16, 2004

Filed:

Mar 26, 1999

Appl. No.:

09/276878

Inventors:

John Francis McNally - Cupertino CA
Jeff Jang-Fang Suen - San Jose CA
Henry Choy - Cupertino CA
Paul Cheng - Fremont CA
Lin Liang - Montain View CA

Assignee:

TVIA, Inc. - Santa Clara CA

International Classification:

H04N 974

US Classification:

348584, 348589, 348598, 348391, 348600

Abstract:

A single chip system including a first input channel for receiving digital video input data, a second channel for receiving computer graphics data, means for synchronizing the two channels to one another utilizing timing signals which may be selected to provide the most accurate timing available, means for changing the rate of presentation of the computer graphics signals to match the rate of presentation of the video signals, means for adjusting the format in which the computer graphics signals are presented to the same format as the format in which the video signals are presented, and means for selectively blending the computer graphics and video signals furnished as video input data without modification for presentation on a single output display.

US Patent:

6772301, Aug 3, 2004

Filed:

Jun 20, 2002

Appl. No.:

10/177895

Inventors:

Paul Cheng - San Jose CA
Nelson L. Chow - Mountain View CA

Assignee:

Integrated Silicon Solution, Inc. - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711159, 711108, 711133

Abstract:

A fast aging system ( ) which may work with a memory ( ) in which data words ( ) having aging words ( ) are stored. An aging address counter ( ) selects an aging word ( ) for updating based on a state change in a linear feedback shift register (LFSR) ( ). Optionally, in the aging word ( ) a zero value ( ) may represent a permanent data words ( ), a predefined non-zero value ( ) may represent data words ( ) which are available for replacement, and other zero values may represent data words ( ) which are in various stages of valid lifetimes and which should not be replaced yet.

US Patent:

6889225, May 3, 2005

Filed:

Aug 9, 2001

Appl. No.:

09/927599

Inventors:

Paul Cheng - San Jose CA, US
Nelson L. Chow - Mountain View CA, US
Fangli Chien - San Jose CA, US

Assignee:

Integrated Silicon Solution, Inc. - Santa Clara CA

International Classification:

G06F007/00

US Classification:

707100

Abstract:

A hash-CAM (H-CAM) which may work with a controller and a memory containing a database of either search values and associate content or associate content by itself The H-CAM includes at least one set of paired hash units and CAM units and at least one logic unit. The CAM units hold values known to cause hash collisions in the respectively paired hash units, and the logic unit prioritizes the hash and CAM unit outputs to a single address value usable to access the memory and obtain a search result at the controller that is not the result of a hash collision. The H-CAM may optionally include a search data storage to store the search values, so that they need not be stored in the memory, and a comparator to determine and handle newly determined hash collisions.

US Patent:

6917934, Jul 12, 2005

Filed:

Sep 30, 2002

Appl. No.:

10/065261

Inventors:

Paul Cheng - San Jose CA, US
Nelson L. Chow - Mountain View CA, US
Fangli Chien - San Jose CA, US

Assignee:

Integrated Silicon Solution, Inc. - Santa Clara CA

International Classification:

G06F017/30

US Classification:

707 3, 707 4, 707 5

Abstract:

A search engine () having a controller (), a memory (), and a hash pointer unit (). The memory () includes a database of search data and associate content, and the controller () uses individual search values to access the memory () to obtain individual search results. The controller () includes a hash function () that generates a hash value from a, typically large, search value into a, typically smaller, hash value that may be a hash collision. The controller () converts the hash value into a hash address which is communicated to the hash pointer unit (), which receives the hash address and provides a hash pointer that is communicated to and used by the memory to look up respective search results. In this manner hash collisions are avoided and the size of the memory () is not a function of the degree of multi-way set-associativity used.

US Patent:

6925524, Aug 2, 2005

Filed:

Mar 20, 2003

Appl. No.:

10/249189

Inventors:

Nelson L. Chow - Mountain View CA, US
David L. Amey - Los Angeles CA, US
Paul Cheng - San Jose CA, US

Assignee:

Integrated Silicon Solution, Inc. - Santa Clara CA

International Classification:

G06F012/08

US Classification:

711108

Abstract:

A relocation system to associatively search a database lookup table with a search key to addressably retrieve a corresponding associate content table record as a search result. The relocation system is implemented in search engine devices having associative memory (e. g. , CAM) having one or more sections. The search engine devices employ relocation values when calculating addresses, one per section per device, with the relocation values optionally pre-calculated and stored in relocation registers. The search engine devices may be cascaded to construct a larger search engine. The search engine is typically used with a processor and addressable memory (e. g. , RAM or ROM). In particular, the relocation system permits multiple databases to be concurrently stored and worked with in the associative and addressable memory.