Paul B Ekas

US Patent:

8327154, Dec 4, 2012

Filed:

Apr 29, 2011

Appl. No.:

13/097918

Inventors:

Dirk A. Reese - Campbell CA, US
Paul B. Ekas - Redwood City CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 11/30
H03K 19/177

US Classification:

713187, 713189, 713193, 326 39, 326 8

Abstract:

A method to configure a programmable device is disclosed. The method includes receiving a scrambled configuration data at the programmable device. A bit sequence of a device tag that is stored in the programmable device is verified by determining whether the bit sequence of the device tag stored in the programmable device matches a bit sequence of a device tag within the scrambled configuration data. If the bit sequences match, the scrambled configuration data is transferred to a data re-formatter for descrambling. The descrambled configuration data is then transferred to a configuration memory of the programmable device. Circuitry that enables the method is also disclosed.

US Patent:

8537956, Sep 17, 2013

Filed:

Nov 24, 2010

Appl. No.:

12/954514

Inventors:

Tien Duc Pham - San Jose CA, US
Leon Zheng - San Francisco CA, US
Zhi Y. Wong - San Jose CA, US
Paul B. Ekas - Redwood City CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03D 3/24

US Classification:

375376, 375373, 375371, 375354, 375316

Abstract:

A demultiplexer circuit separates input data having different data rates into output data. A phase-locked loop circuit generates first clock signals having average frequencies that are based on a frequency of a second clock signal times a fractional, non-integer number. A serializer circuit serializes a set of the output data to generate serial data signals in response to one of the first clock signals generated by the phase-locked loop circuit.

US Patent:

20120221919, Aug 30, 2012

Filed:

Feb 25, 2011

Appl. No.:

13/035826

Inventors:

Paul B. Ekas - Redwood City CA, US
David Lewis - Toronto, CA

International Classification:

H03M 13/29
G06F 11/10

US Classification:

714758, 714E11034

Abstract:

Integrated circuits with memory circuitry may include error detection circuitry and error correction circuitry. The error detection circuitry may be used to detect soft errors in the memory circuitry. The error detection circuitry may include logic gates that are used to perform parity checking. The error detection circuitry may have an interleaved structure to provide interleaved data bit processing, may have a tree structure to reduce logic gate delays, and may be pipelined to optimize performance. The memory circuitry may be loaded with interleaved parity check bits in conjunction with the interleaved structure to provide multi-bit error detection capability. The parity check bits may be precomputed using design tools or computed during device configuration. In response to detection of a memory error, the error correction circuitry may be used to scan desired portions of the memory circuitry and to correct the memory error.

US Patent:

53509536, Sep 27, 1994

Filed:

May 28, 1993

Appl. No.:

8/069943

Inventors:

Richard M. Swenson - Ridgecrest CA
John C. Cole - Mercer Island WA
Steve L. Holmes - Redmond WA
Paul B. Ekas - Seattle WA

International Classification:

H03K 1923
H03K 1908

US Classification:

307464

Abstract:

A neuron for an artificial neural network provides digital weighting of input signals at a common portion of the neuron rather than at each synapse. The neuron is adapted for use of differential signals, and the weighting may be provided by field effect transistors of different widths, by subtracting a plurality of differential signal components from an opposite most significant component, or by subtracting one half of a differential signal component from the opposite next most significant component. The neuron may provide binary sign selection and digit selection by switching input and reference signals at each synapse.

US Patent:

20160375589, Dec 29, 2016

Filed:

Sep 9, 2016

Appl. No.:

15/261690

Inventors:

Paul Ekas - Redwood City CA, US

International Classification:

B25J 15/00
B25J 15/10

Abstract:

A robotic gripper includes a gripper palm, a first pair of adjacent fingers extending from the palm, each finger in the first pair of fingers including a first link coupled to a second link by a rotatable joint, and a second pair of adjacent fingers extending from the palm, each finger in the second pair of fingers including a first link coupled to a second link by a rotatable joint. A web member is attached to the first pair of adjacent fingers, the web member having a web portion having a gripping face, the web portion disposed between a first one of the first pair of adjacent fingers and a second one of the second pair of adjacent fingers.

US Patent:

20160052129, Feb 25, 2016

Filed:

Aug 25, 2015

Appl. No.:

14/835351

Inventors:

Paul Ekas - Redwood City CA, US

International Classification:

B25J 9/10
B25J 9/06

Abstract:

A robotic mechanical manipulator structure includes a first link and a second link rotatably coupled to the first link by a rotatable joint. A first high hardness cable guide is disposed in the first link. A first cable is connected between the first link and the second link to move the first link relative to the second link in a first direction around the joint, the first cable connected to the first link at a first anchor point, and passing through the first high hardness cable guide in the second link.

US Patent:

20160052130, Feb 25, 2016

Filed:

Aug 24, 2015

Appl. No.:

14/834178

Inventors:

Paul Ekas - Redwood City CA, US

International Classification:

B25J 9/10
B25J 9/06

Abstract:

A robotic mechanical manipulator structure includes a first link, a second link rotatably coupled to the first link, a first cable connected between the first link and the second link and coupled to the first link by a spring anchored to the first link, passing through cable guides on the first link and the second link and anchored to the second link, and a second cable connected between the first link and the second link and anchored to the first link, passing through cable guides on the first link and the second link and coupled to an actuator. The cables each have a length selected to provide a selected range of motion between the second link at a selected angle with respect to the first link when the actuator is in a rest position. The cable guides are formed from a high hardness material.

US Patent:

20160052142, Feb 25, 2016

Filed:

Aug 24, 2015

Appl. No.:

14/833798

Inventors:

Paul Ekas - Redwood City CA, US

International Classification:

B25J 15/00
B25J 15/08

Abstract:

A robot mechanism includes a link formed from a first segment abutting a second segment at opposing faces thereof, at least one tendon passing from the first segment into the second segment, wherein the first segment is held in contact with the second segment by tension applied to the at least one segment.