Paul O Foster

US Patent:

6721922, Apr 13, 2004

Filed:

Sep 27, 2001

Appl. No.:

09/965676

Inventors:

Don Walters - Aptos CA
Paul Foster - Aptos CA
Tina Najibi - San Jose CA

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 1750

US Classification:

716 1, 716 4, 716 5, 716 6, 716 18

Abstract:

A system is herein disclosed which allows for the interactive design and analysis of analog and mixed-signal circuits. Circuits may additionally be characterized and verified without leaving the environment provided by the system. The system may be used to analyze multiple circuit designs at the same time. In this manner a designer can create a test that sweeps over several circuit designs. Embodiments of the invention may be integrated with other circuit design tools and development systems.

US Patent:

6832358, Dec 14, 2004

Filed:

Dec 18, 2002

Appl. No.:

10/322854

Inventors:

Paul C. Foster - Scotts Valley CA
James Britton - San Jose CA
Alan Mayes - Fareham, GB
Richard E. Seiter - Santa Cruz CA

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 1750

US Classification:

716 4, 716 5, 716 6, 705 59, 705 51, 705 57

Abstract:

A system and method which allows for burst licensing, particularly for use in a circuit design and analysis system in which designers use tools to assist in characterizing and verifying the circuit. Burst licensing is used to provide licenses on an âas and when requiredâ basis to allow system users or customers to carry out massive parallelism of the simulation tasks when run from selected tools. When the system receives a request to start a task, the system checks-out a burst license for use in processing the task, and assigns the license to a particular CPU. The task is then performed at that CPU, and once completed the burst license is returned to the license pool.

US Patent:

7299429, Nov 20, 2007

Filed:

Dec 2, 2004

Appl. No.:

11/002719

Inventors:

Paul C. Foster - Scotts Valley CA, US
James Britton - San Jose CA, US
Alan Mayes - Fareham, GB
Richard E. Seiter - Santa Cruz CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 4, 716 5, 716 6, 705 59

Abstract:

A system and method which allows for burst licensing, particularly for use in a circuit design and analysis system in which designers use tools to assist in characterizing and verifying the circuit. Burst licensing is used to provide licenses on an ‘as and when required’ basis to allow system users or customers to carry out massive parallelism of the simulation tasks when run from selected tools. When the system receives a request to start a task, the system checks-out a burst license for use in processing the task, and assigns the license to a particular CPU. The task is then performed at that CPU, and once completed the burst license is returned to the license pool.

US Patent:

8327303, Dec 4, 2012

Filed:

Jan 22, 2010

Appl. No.:

12/692497

Inventors:

Paul C. Foster - Scotts Valley CA, US
Walter E. Hartong - Isen, DE
T. Martin O'Leary - San Jose CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716106

Abstract:

A method and system for template-based behavioral model creation for behavioral modeling is disclosed. A design characterization and modeling (DCM) tool has a number of templates for different circuits. A designer chooses a template and customizes the template with a number of parameters and optionally pin assignments. The DCM tool generates a behavioral model that has real wire (“Wreal”) capability. The transistor level design is simulated with a testbench according to the parameters to generate Wreal calibration information. The behavioral model uses the Wreal calibration information in behavioral modeling to provide quick behavioral processing of the behavioral model with the benefit of increased accuracy provided by the Wreal calibration information, for example. Optionally, the DCM tool generates another testbench that validates the analog and behavioral models.

US Patent:

8423934, Apr 16, 2013

Filed:

Feb 22, 2010

Appl. No.:

12/710212

Inventors:

Paul C. Foster - Scotts Valley CA, US
Tina M. Najibi - San Jose CA, US
Walter E. Hartong - Isen, DE
T. Martin O'Leary - San Jose CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716107

Abstract:

An electronic design automation (EDA) tool to validate representations of a design is disclosed. Reference and compared representations of the design are intended to respond to stimulus in the same way, but at different levels of abstraction. The reference and compared representations are simulated, at some point, to each generate waveform signals and measured results. Simulation can be with the same tool or different tools. The same or different testbench can be used on the reference and compared representations in the simulation. A design representation validation function compares the two sets of generated waveform signals and compares the two sets of measured results to identify any violations. The measured results and/or waveform signals could be loaded from previous simulations and just validated within the validation tool. Loaded simulations could be for the reference representation with just simulation of the compared representation by the validation tool, or for both with no simulations run by the validation tool.

US Patent:

55419216, Jul 30, 1996

Filed:

Dec 6, 1994

Appl. No.:

8/349977

Inventors:

Erik R. Swenson - San Jose CA
Paul Foster - San Jose CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H04Q 1108

US Classification:

370 68

Abstract:

A serial time division multiplexer routes data from a plurality of isochronous data sources to a plurality of isochronous data sinks without buffering the data in a random-access memory by utilizing a plurality of selectors that each select predetermined time slots from a plurality of incoming isochronous data streams. Each selector selects which time slots are to be received in response to a sequence of selection codes. A control stage controls the timing of the selection codes so that each selector receives a selection code when the time slot that corresponds to that selection code is received.