Paul E Gray

US Patent:

7673213, Mar 2, 2010

Filed:

Aug 12, 2005

Appl. No.:

11/203683

Inventors:

Keith Michael Chugg - La Canada CA, US
Paul Kingsley Gray - San Diego CA, US

Assignee:

Trellisware Technologies, Inc. - San Diego CA

International Classification:

H03M 13/00
H03M 13/03

US Classification:

714755, 714790

Abstract:

Methods, apparatuses, and systems are presented for performing data encoding involving encoding data bits according to an outer convolutional code to produce outer encoded bits, processing the outer encoded bits using an interleaver and a single parity check (SPC) module to produce intermediate bits, encoding the intermediate bits according to an inner convolutional code to produce inner encoded bits, processing the inner encoded bits using a puncture module to produce punctured bits, and combining the data bits and the punctured bits to produce encoded outputs. Methods, apparatuses, and systems are also presented for performing data decoding based on soft channel metrics derived from a channel using various iterative techniques.

US Patent:

7958425, Jun 7, 2011

Filed:

Feb 16, 2005

Appl. No.:

11/060081

Inventors:

Keith Michael Chugg - La Canada CA, US
Paul Kingsley Gray - San Diego CA, US
Georgios Dimitrios Dimou - San Diego CA, US
Phunsak Thiennviboon - San Diego CA, US

Assignee:

Trelliware Technologies, Inc. - San Diego CA

International Classification:

H03M 13/00

US Classification:

714755

Abstract:

The present invention relates to methods, apparatuses, and systems for performing data encoding involving encoding data bits according to an outer convolutional code to produce outer encoded bits processing the outer encoded bits using an interleaver and a logical unit to produce intermediate bits, wherein the logical unit receives a first number of input bits and produces a second number of corresponding output bits, the second number being less than the first number, and wherein the logical unit takes each of the first number of input bits into account in producing the second number of output bits, encoding the intermediate bits according to an inner convolutional code to produce inner encoded bits, wherein the inner convolutional code is characterized by at least two states, and combining the data bits and the inner encoded bits to produce encoded outputs.

US Patent:

20070259075, Nov 8, 2007

Filed:

May 4, 2006

Appl. No.:

11/418012

Inventors:

Paul Gray - Venice CA, US

International Classification:

B65D 85/00

US Classification:

426091000

Abstract:

A confection support holder is disclosed. The confection support holder includes, a support chamber, a resilient insulation cover, an outer support cover, a plurality of protrusions and a reservoir. The resilient insulation cover includes a second resilient insulation side contacting said support chamber and a first resilient insulation side. The outer support cover includes a first cover side contacting a confection and a second cover side contacting said first resilient insulation side, a bottom cover portion, a top cover portion and a body cover portion. The plurality of protrusions contact said first cover side of said outer support cover and contact said confection, providing support. The reservoir, including a plurality of ridge members, is sealed to said bottom cover portion, providing protection from said confection dripping.

US Patent:

20120284622, Nov 8, 2012

Filed:

May 6, 2011

Appl. No.:

13/102458

Inventors:

Ryan L. Avery - San Francisco CA, US
Stephen Crocker - Tyngsboro MA, US
Paul J. Gray - Cambridge MA, US

International Classification:

G06F 3/048

US Classification:

715719, 715716

Abstract:

Methods and systems for providing media editing capability to a user of a mobile device in communication with a video or an audio media editing system. The methods involve receiving at the mobile device information specifying a current user context of the media editing system and automatically activating functionality on the mobile device that corresponds to the current editing context. The functionality may be a subset of the editing system controls, controls associated with a plug-in software module, or new controls or control modalities enabled by the form factor and input modes featured on the mobile device. The functionality of the mobile device may be updated as the editing context changes, or temporarily frozen to enable multi-user work flows, with each user using a different editing function.

US Patent:

41298632, Dec 12, 1978

Filed:

Oct 3, 1977

Appl. No.:

5/838908

Inventors:

Paul R. Gray - Orinda CA
James L. McCreary - Red Bank NJ
David A. Hodges - Berkeley CA

Assignee:

Regents of the University of California - Berkeley CA

International Classification:

H03K 1302

US Classification:

340347AD

Abstract:

An array of binary weighed capacitors, an additional capacitor having a capacitance value equivalent to that of the least of the binary weighted capacitors, a voltage comparator, switches for interconnecting the capacitors with certain predetermined voltage levels and the comparator, and a sequencing circuit are included. One side of all of the capacitors is connected to one input terminal on the comparator and the other side has applied thereto the signal to be quantized. Switch sequencing combines divided portions of a reference voltage with the signal to be quantized for presentation to the input of the comparator which thereby provides a serial digit output connected to the sequencing circuit. In this fashion, a linear conversion between an analog and a digital signal is made by the sequencing circuit. A nonlinear converter between digital and analog signal presentation is also disclosed.

US Patent:

42008638, Apr 29, 1980

Filed:

Dec 11, 1978

Appl. No.:

5/968590

Inventors:

David A. Hodges - Berkeley CA
Paul R. Gray - Orinda CA
James L. McCreary - Santa Clara CA

Assignee:

The Regents of the University of California - CA

International Classification:

H03K 1302

US Classification:

340347AD

Abstract:

An array of binary weighted capacitors, an additional capacitor having a capacitance value equivalent to that of the least of the binary weighted capacitors, a voltage comparator, switches for interconnecting the capacitors with certain predetermined voltage levels and the comparator, and a sequencing circuit are included. One side of all of the capacitors is connected to one input terminal on the comparator and the other side has applied thereto the signal to be quantized. Switch sequencing combines divided portions of a reference voltage with the signal to be quantized for presentation to the input of the comparator which thereby provides a serial digit output connected to the sequencing circuit. In this fashion, a linear conversion between an analog and a digital signal is made by the sequencing circuit. A nonlinear converter between digital and analog signal presentation is also disclosed.

US Patent:

48976113, Jan 30, 1990

Filed:

Oct 28, 1988

Appl. No.:

7/264401

Inventors:

Carlos A. Laber - Los Altos CA
Paul R. Gray - Orinda CA

Assignee:

Micro Linear Corporation - San Jose CA

International Classification:

H03F 138
H03F 316

US Classification:

330253

Abstract:

This invention is for a transconductance amplifier. The amplifier has an amplifier input and an amplifier output with an amplifier output impedance. An input stage of the amplifier has a first transconductance. An intermediate state is coupled to the amplifier output through positive feedback. The intermediate stage has a second transconductance and an intermediate stage output having an intermediate output impedance. The gain of the amplifier is a function of the first transconductance times the second transconductance times the amplifier output impedance times the intermediate output impedance.

US Patent:

41684400, Sep 18, 1979

Filed:

Jan 12, 1978

Appl. No.:

5/868976

Inventors:

Paul R. Gray - Orinda CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03H 1100

US Classification:

307233R

Abstract:

An active filter employing a plurality of integrators which may be fabricated as a metal-oxide-semiconductor (MOS) integrated circuit is described. S-plane zeros are obtained without additional active devices when compared to prior art filters without such zeros. The zeros result from resistive coupling between the integrators. Resistance ratios and capacitance ratios primarily determine the filter's characteristics rather than the absolute value of these elements. This permits the filter to be readily fabricated with existing MOS technology.