Paul W Gray

US Patent:

20120284622, Nov 8, 2012

Filed:

May 6, 2011

Appl. No.:

13/102458

Inventors:

Ryan L. Avery - San Francisco CA, US
Stephen Crocker - Tyngsboro MA, US
Paul J. Gray - Cambridge MA, US

International Classification:

G06F 3/048

US Classification:

715719, 715716

Abstract:

Methods and systems for providing media editing capability to a user of a mobile device in communication with a video or an audio media editing system. The methods involve receiving at the mobile device information specifying a current user context of the media editing system and automatically activating functionality on the mobile device that corresponds to the current editing context. The functionality may be a subset of the editing system controls, controls associated with a plug-in software module, or new controls or control modalities enabled by the form factor and input modes featured on the mobile device. The functionality of the mobile device may be updated as the editing context changes, or temporarily frozen to enable multi-user work flows, with each user using a different editing function.

US Patent:

20140048978, Feb 20, 2014

Filed:

Aug 16, 2012

Appl. No.:

13/586930

Inventors:

Glenn Curtis Taxacher - Simpsonville SC, US
Peter de Diego - Saluda NC, US
Paul Edward Gray - North East MD, US
Philip Harold Monaghan - Hockessin DE, US

Assignee:

GENERAL ELECTRIC COMPANY - Schenectady NY

International Classification:

B29C 33/52
B29C 39/02

US Classification:

264317, 249 61

Abstract:

Systems, methods and devices adapted to ease manufacture of composite articles (e.g., ceramic composite articles), particularly composite articles which include a hollow feature are disclosed. In one embodiment, a system includes: a consumable core formed to be disposed within an inner portion of a composite precursor, the consumable core adapted to convert into an infiltrant during a manufacturing process and infiltrate the composite precursor.

US Patent:

41298632, Dec 12, 1978

Filed:

Oct 3, 1977

Appl. No.:

5/838908

Inventors:

Paul R. Gray - Orinda CA
James L. McCreary - Red Bank NJ
David A. Hodges - Berkeley CA

Assignee:

Regents of the University of California - Berkeley CA

International Classification:

H03K 1302

US Classification:

340347AD

Abstract:

An array of binary weighed capacitors, an additional capacitor having a capacitance value equivalent to that of the least of the binary weighted capacitors, a voltage comparator, switches for interconnecting the capacitors with certain predetermined voltage levels and the comparator, and a sequencing circuit are included. One side of all of the capacitors is connected to one input terminal on the comparator and the other side has applied thereto the signal to be quantized. Switch sequencing combines divided portions of a reference voltage with the signal to be quantized for presentation to the input of the comparator which thereby provides a serial digit output connected to the sequencing circuit. In this fashion, a linear conversion between an analog and a digital signal is made by the sequencing circuit. A nonlinear converter between digital and analog signal presentation is also disclosed.

US Patent:

42008638, Apr 29, 1980

Filed:

Dec 11, 1978

Appl. No.:

5/968590

Inventors:

David A. Hodges - Berkeley CA
Paul R. Gray - Orinda CA
James L. McCreary - Santa Clara CA

Assignee:

The Regents of the University of California - CA

International Classification:

H03K 1302

US Classification:

340347AD

Abstract:

An array of binary weighted capacitors, an additional capacitor having a capacitance value equivalent to that of the least of the binary weighted capacitors, a voltage comparator, switches for interconnecting the capacitors with certain predetermined voltage levels and the comparator, and a sequencing circuit are included. One side of all of the capacitors is connected to one input terminal on the comparator and the other side has applied thereto the signal to be quantized. Switch sequencing combines divided portions of a reference voltage with the signal to be quantized for presentation to the input of the comparator which thereby provides a serial digit output connected to the sequencing circuit. In this fashion, a linear conversion between an analog and a digital signal is made by the sequencing circuit. A nonlinear converter between digital and analog signal presentation is also disclosed.

US Patent:

41684400, Sep 18, 1979

Filed:

Jan 12, 1978

Appl. No.:

5/868976

Inventors:

Paul R. Gray - Orinda CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03H 1100

US Classification:

307233R

Abstract:

An active filter employing a plurality of integrators which may be fabricated as a metal-oxide-semiconductor (MOS) integrated circuit is described. S-plane zeros are obtained without additional active devices when compared to prior art filters without such zeros. The zeros result from resistive coupling between the integrators. Resistance ratios and capacitance ratios primarily determine the filter's characteristics rather than the absolute value of these elements. This permits the filter to be readily fabricated with existing MOS technology.

US Patent:

40500314, Sep 20, 1977

Filed:

Mar 1, 1976

Appl. No.:

5/662462

Inventors:

Paul R. Gray - Orinda CA
Mark L. Stephens - Campbell CA

Assignee:

Signetics Corporation - Sunnyvale CA

International Classification:

H03F 310
H03F 316

US Classification:

330 24

Abstract:

An amplifier circuit and structure having high input impedance and having a return path for conducting amplifier DC leakage current. A common diode structure forms the return path and includes two diodes connected in series and connected in opposite conduction directions. The diode having a forward conduction direction which is in the opposite direction of the leakage current is provided with a reverse saturation current which is substantially greater than the leakage current of the amplifier. The amplifier is typically a P channel or N channel field effect transistor (FET) and the double diode structure is typically an NPN or PNP transistor.

US Patent:

47423307, May 3, 1988

Filed:

May 1, 1987

Appl. No.:

7/045349

Inventors:

Joey Doernberg - Berkeley CA
Paul R. Gray - Orinda CA
David A. Hodges - Berkeley CA

Assignee:

The Regents of the University of California - Berkeley CA

International Classification:

H03M 112

US Classification:

340347AD

Abstract:

A flash ADC utilizes parallel weighted capacitive arrays and a resistor string to provide reference voltage intervals and an encoder for indicating the reference voltage interval wherein an input voltage lies. For an embodiment having N branches, the reference voltage intervals are subdivided into N sub-intervals and each succeeding clock cycle.

US Patent:

46225366, Nov 11, 1986

Filed:

Sep 28, 1984

Appl. No.:

6/655642

Inventors:

Cheng-Chung Shih - Albany CA
Paul R. Gray - Orinda CA

Assignee:

Regents of the University of California - Berkeley CA

International Classification:

H03M 106
H03M 140

US Classification:

340347DA

Abstract:

An algorithmic analog-to-digital and digital-to-analog converter 10 combines the techniques of switched capacitor cyclic conversion by using first and second amplifiers 31, 32 with capacitors C. sub. 1, C. sub. 1 ', C. sub. 2, C. sub. 2 ', C. sub. 3, C. sub. 3 ', C. sub. 4, C. sub. 4 ', C. sub. 5, C. sub. 5 ' communicating with the inputs of said amplifiers 31, 32 and between the inputs and outputs of said amplifiers 31, 32, and the techniques of reference voltage refreshing. The performance of the converter 10 is capacitor ratio-independent. Because of the ratio-independent aspect, very small component values can be used, and as a result, the die area required for the circuitry can be quite small.