Paul D Hendricks

US Patent:

6408031, Jun 18, 2002

Filed:

Oct 27, 1999

Appl. No.:

09/428086

Inventors:

Paul David Hendricks - Coopersburg PA

Assignee:

Agere Systems Guardian Corp. - Orlando FL

International Classification:

H04B 1406

US Classification:

375247, 375350, 341143, 341144, 341155, 708307

Abstract:

A digital system for filtering a single bit input signal according to the transfer function H(z), wherein H(z) has a gain G, a pole at location b , and a zero at location a. The digital system filters the single bit input signal without using computationally expensive multibit multiplication. The digital system achieves these advantages with a digital circuit having a first gain stage generating a gain corrected signal, a delay element generating a delayed gain corrected signal, a feed-forward stage generating a feed-forward signal, and a summer for generating an output signal based upon the sum of the gain corrected signal, the delayed gain corrected signal and the feed-forward signal.

US Patent:

6625278, Sep 23, 2003

Filed:

Aug 24, 1999

Appl. No.:

09/379603

Inventors:

Paul D. Hendricks - Coopersburg PA
Donald R. Laturell - Allentown PA
Lane A. Smith - Easton PA
Steven B. Witmer - Spring Township, Berks County PA

Assignee:

Agere Systems Guardian Corp. - Allentown PA

International Classification:

H04M 100

US Classification:

379398, 379394, 37939901

Abstract:

An AC impedance matching architecture which provides programmable AC impedance matching in a given range using a digital filter to filter a signal fed back from the impedance matched line to generate an AC impedance emulation control signal. The AC impedance emulation control signal is combined with a transmit signal (if desired) and drives a voltage controlled current source, which is in parallel with a reference impedance. A voltage is developed across the reference impedance to drive, e. g. , the telephone line. The reference impedance is chosen based on a desired maximum AC impedance. The gain of the digital filter, a first order sigma delta filter in the disclosed embodiment, is chosen based on the desired value of the AC impedance. The transfer function of the digital filter is derived based on a desired AC impedance.

US Patent:

6674856, Jan 6, 2004

Filed:

Sep 23, 1999

Appl. No.:

09/401995

Inventors:

Paul D. Hendricks - Coopersburg PA
Donald R. Laturell - Allentown PA
Lane A. Smith - Easton PA
Steven B. Witmer - Spring Township, Berks County PA

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H04M 100

US Classification:

37939901, 379 9305, 379402, 375254, 375285, 375296

Abstract:

The present invention provides a digital pre-distortion filter in arrangement with a data access arrangement (DAA) on the component side (e. g. , in a modem chipset). This arrangement of the pre-distortion filter outside of the DAA allows digital processes such as digital emulation of the central office impedance to remain unaffected by the pre-distortion in the transmitted signal, allowing the dynamic range of the transmitted signal to be flattened to minimize return loss without complicating the transfer function of the digital emulation of the central office complex load. In the case of a digital emulation filter, placement of a digital pre-distortion filter outside of an analog-to-digital (A/D) digital-to-analog (D/A) loop also minimizes the noise otherwise associated with the use of a pre-distortion filter. Thus, benefits of a pre-distortion filter can be gained without interfering with emulation of impedance, and without causing a significant amount of noise in the transmitted signal.

US Patent:

20070028488, Feb 8, 2007

Filed:

Jul 19, 2005

Appl. No.:

11/160990

Inventors:

Brad Bilinsky - Greenfield PA, US
Paul Hendricks - Scranton PA, US

International Classification:

E02F 3/96

US Classification:

037468000

Abstract:

The present invention provides for a bracket assembly mountable to an articulated arm. The mountable bracket assembly allows for efficient transfer of a working end attachment while causing minimal or no incidental environmental damage during the loading/unloading process. The bracket assembly comprises a mounting assembly mounted to the underside side of an articulated arm and a pivot piece assembly pivotally mounted to the mounting assembly. An optional stabilizer is dimensionally fabricated to effectively capture and stabilize a portion of the working end attachment when positioned for transport.

US Patent:

53172086, May 31, 1994

Filed:

May 12, 1992

Appl. No.:

7/881595

Inventors:

Dennis C. Banker - Newburgh NY
Tore A. Carlson - Brewster NY
Jack A. Dorler - Holmes NY
Paul D. Hendricks - Whitehall PA
Walter S. Klara - Hopewell Junction NY
Frank M. Masci - Wappingers Falls NY
James R. Struk - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 19013

US Classification:

307454

Abstract:

Relatively constant current sources and current mirrors are formed with vertical bipolar transistors operated in the inverse mode. In one embodiment of the invention, an integrated circuit current mirror includes a dual collector vertical NPN bipolar transistor having first and second regions of one conductivity type defining first and second collector regions, respectively, formed within a common third region of opposite conductivity type defining the base of the transistor. The third region is formed within a fourth region defining the emitter of the transistor. The structure of the dual collector vertical transistor is very compact since the two collectors share the same base region which is embedded in a common emitter (inverse collector) pocket. The "inverse" mode vertical transistor can function as a relatively constant current source with a voltage drop (VCEi) across its collector-to-emitter which is substantially less than that of a bipolar transistor operated in a normal mode. Transistors embodying the invention may be used to provide relatively constant current sources to numerous utilization means, such as logic or analog circuits.

US Patent:

6215429, Apr 10, 2001

Filed:

Jan 19, 1999

Appl. No.:

9/232221

Inventors:

Jonathan Herman Fischer - Blandon PA
Donald Raymond Laturell - Allentown PA
Lane A. Smith - Easton PA
Paul David Hendricks - Coopersburg PA
James M. Little - Sacramento CA

Assignee:

Lucent Technologies, Inc. - Murray Hill NJ

International Classification:

H03M 162

US Classification:

341139

Abstract:

An integrated circuit, e. g. an AC '97 conforming audio codec, includes a digital filter and gain module including multiple channels of gain control and multiple channels of digital filtering. A gain control module includes an overflow check of data samples requiring differing lengths of clamping. Each channel of the digital filter includes a finite impulse response (FIR) filter, and an infinite impulse response (IIR) filter. The digital filtering is implemented largely in hardware independent of the number of channels required and/or independent of the required order of the filtering. Thus, filter channels can be added or additional filtering implemented merely by increasing the clock speed without changing the digital filter design. The FIR filter is capable of being reset each frame to prevent a DC buildup at internal nodes. The IIR filter performs a plurality of 2. sup.

US Patent:

59991143, Dec 7, 1999

Filed:

Sep 16, 1997

Appl. No.:

8/976105

Inventors:

Paul David Hendricks - Coopersburg PA

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

H03M 120

US Classification:

341131

Abstract:

A method of breaking up idle tones in a converter is used for gain scaling and summing of digital input signals. The invention achieves this object by introducing dither. Further, the invention optimizes the dither introduced by adapting the magnitude of the dither based on the value of the feedback gain factor of the converter. By adapting the dither in this way, the output idle channel noise can be essentially constant and independent of the scaling factor of the converter.

US Patent:

61157317, Sep 5, 2000

Filed:

Apr 7, 1998

Appl. No.:

9/056722

Inventors:

Paul D. Hendricks - Whitehall PA

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

G06F 738

US Classification:

708552

Abstract:

A scalable overflow clamp for controlling the level of allowable digital signal overflow in a gain scaler/summer having an initial full-scale range and a feedback path for establishing a feedback gain. The clamp includes a range scaler for determining the feedback gain and generating a modified full-scale range relative to the feedback gain. The modified full-scale range defines a substantially constant overflow capability relative to the feedback gain. An overflow detector senses the overflow conditions and a selector responsive to the overflow detector utilizes the modified full-scale range when overflow conditions are sensed.