Paul N Hendricks

US Patent:

53172086, May 31, 1994

Filed:

May 12, 1992

Appl. No.:

7/881595

Inventors:

Dennis C. Banker - Newburgh NY
Tore A. Carlson - Brewster NY
Jack A. Dorler - Holmes NY
Paul D. Hendricks - Whitehall PA
Walter S. Klara - Hopewell Junction NY
Frank M. Masci - Wappingers Falls NY
James R. Struk - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 19013

US Classification:

307454

Abstract:

Relatively constant current sources and current mirrors are formed with vertical bipolar transistors operated in the inverse mode. In one embodiment of the invention, an integrated circuit current mirror includes a dual collector vertical NPN bipolar transistor having first and second regions of one conductivity type defining first and second collector regions, respectively, formed within a common third region of opposite conductivity type defining the base of the transistor. The third region is formed within a fourth region defining the emitter of the transistor. The structure of the dual collector vertical transistor is very compact since the two collectors share the same base region which is embedded in a common emitter (inverse collector) pocket. The "inverse" mode vertical transistor can function as a relatively constant current source with a voltage drop (VCEi) across its collector-to-emitter which is substantially less than that of a bipolar transistor operated in a normal mode. Transistors embodying the invention may be used to provide relatively constant current sources to numerous utilization means, such as logic or analog circuits.

US Patent:

52412237, Aug 31, 1993

Filed:

May 12, 1992

Appl. No.:

7/881592

Inventors:

Dennis C. Banker - Newburgh NY
Jack A. Dorler - Holmes NY
Paul D. Hendricks - Whitehall PA
Frank M. Masci - Wappingers Falls NY
Stephen J. Tytran - Pleasant Valley NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 301

US Classification:

307455

Abstract:

NOR logic performed by a half current switch emitter follower ("HCSEF") circuit utilizing a transistor operated in the inverse active mode as its current source and having logic levels compatible with those of current switch emitter follower ("CSEF") circuitry is combined with a novel reference bias generator that controls the logic low voltage level by controlling the voltage drop across the current source. The NOR. sub. i circuit utilizes less power than CSEF circuits, has a natural threshold equal to the threshold of CSEF circuits to which it is coupled, has a delay skew of approximately 1:1, and maintains minimum signal levels with respect to variations on V. sub. cc. The reference bias generator compensates for temperature, process variables and variations in the NOR. sub. i circuit and in the power supply.