Paul D Krivacek

US Patent:

6732235, May 4, 2004

Filed:

Nov 6, 2000

Appl. No.:

09/707239

Inventors:

Paul D. Krivacek - Cambridge MA
Jørn Sørensen - Aars, DK
Frederic Boutaud - Belmont MA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G06F 1200

US Classification:

711118, 711130, 711137, 711147, 712237

Abstract:

A digital signal processing system includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masters each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention. The system further includes a cache memory system allowing one process to perform real-time digital signal processing according to a modifiable program stored in a modifiable non-volatile memory by temporarily loading portions of the program into a fast, local memory.

US Patent:

6738845, May 18, 2004

Filed:

Nov 3, 2000

Appl. No.:

09/706577

Inventors:

Rainer R. Hadwiger - North Andover MA
Paul D. Krivacek - Cambridge MA
Jørn Sørensen - Aars, DK
Palle Birk - Gistrup, DK

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G06F 1338

US Classification:

710240, 710241, 710244, 710306, 710308, 710316, 710317, 710110, 710305

Abstract:

A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masers each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.

US Patent:

6895459, May 17, 2005

Filed:

Sep 10, 2003

Appl. No.:

10/659533

Inventors:

Rainer R. Hadwiger - North Andover MA, US
Paul D. Krivacek - Cambridge MA, US
Jørn Sørensen - Aars, DK
Palle Birk - Gistrup, DK

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G06F013/00

US Classification:

710111, 710116

Abstract:

A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masers each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.

US Patent:

7007132, Feb 28, 2006

Filed:

Aug 29, 2002

Appl. No.:

10/230668

Inventors:

Joern Soerensen - Aars, DK
Paul D. Krivacek - Cambridge MA, US
Michael S. Allen - Austin TX, US
Mark A. Banse - Austin TX, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G06F 12/00

US Classification:

711103, 711167, 711169

Abstract:

Methods and apparatus for accessing flash memory in a continued burst mode are provided. The apparatus includes a processor for executing instructions including memory access instructions, the processor generating a next access signal that indicates if a next memory access is in sequence with a current memory access, a memory having a continued burst mode of operation, and a bus interface for controlling access to the memory in response to the memory access instructions. The bus interface unit enables the continued burst mode of the memory while the next access signal is asserted.

US Patent:

7174543, Feb 6, 2007

Filed:

Aug 29, 2002

Appl. No.:

10/231722

Inventors:

Joerg Schwemmlein - Gloucester MA, US
Paul D. Krivacek - Winchester MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G06F 9/44

US Classification:

717128, 717129, 714 35

Abstract:

A high speed program tracer providing compression using linear increment run length values, displacement values corresponding to discontinuities, and loop compression. A program count sequencer receives program count values from a processor, and outputs various program count values and signals to allow compression calculations to be made based upon linear increment run lengths, discontinuity detection, and detection of repeating instruction loops. Compression may be achieved using selected numbers of words to represent various compression values.

US Patent:

7916841, Mar 29, 2011

Filed:

Oct 11, 2006

Appl. No.:

11/545857

Inventors:

Aiguo Yan - North Andover MA, US
Lidwine Martinot - Cottenham, GB
Marko Kocic - Somerville MA, US
Paul D. Krivacek - North Andover MA, US
John Zijun Shen - Winchester MA, US

Assignee:

MediaTek Inc. - Hsin-Chu

International Classification:

H04M 1/64
H04L 25/49

US Classification:

379 8807, 358 115, 375231, 375286, 375340, 4552781

Abstract:

A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals and includes a joint detector accelerator and a programmable digital signal processor (DSP). The joint detector accelerator is configured to perform front-end processing of first data inputted to the joint detector accelerator and output second data resulting from the front-end processing. The joint detector accelerator is further configured to perform back-end processing using at least third data inputted to the joint detector accelerator. The programmable DSP is coupled to the joint detector accelerator, and the programmable DSP is programmed to perform at least one intermediate processing operation using the second data outputted by the joint detector accelerator. The programmable DSP is further programmed to output the third data resulting from the intermediate processing operation to the joint detector accelerator.

US Patent:

7953958, May 31, 2011

Filed:

Jun 12, 2007

Appl. No.:

11/818055

Inventors:

John Zijun Shen - Winchester MA, US
Paul D. Krivacek - North Andover MA, US
Lidwine Martinot - Cottenham, GB
Aiguo Yan - North Andover MA, US
Marko Kocic - Somerville MA, US

Assignee:

MediaTek Inc. - Hsin-Chu

International Classification:

G06F 15/76
G06F 9/302

US Classification:

712 35, 712222

Abstract:

A joint detection system is configured to perform joint detection of received signals and includes a joint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.

US Patent:

8095699, Jan 10, 2012

Filed:

Sep 29, 2006

Appl. No.:

11/542092

Inventors:

Sachin Garg - Somerville MA, US
Paul D. Krivacek - North Andover MA, US

Assignee:

MediaTek Inc. - Hsin-Chu

International Classification:

G06F 3/00

US Classification:

710 20, 710 3, 710 4, 710 7, 710 8, 710 31, 710 33, 710 62

Abstract:

An interface to transfer data between a host processor and an external coprocessor is provided. The interface may operate in several write modes, in which in a first write mode the write operation is transferred across the interface in two clock cycles and in a second write mode the write operation is transferred across the interface in a single clock cycle. The interface can perform a first read operation initiated by the host processor and a second read operation initiated by the external coprocessor. The interface can include buffers to store read and write operations and clock gates to selectively gate off clock signals provided to the buffers to synchronize transfer of data into and out of the buffers. A selectable priority scheme can be modified to select between priorities that control a preference in transferring operations over the interface when both read and write operations are queued for transfer.