Paul S Lin

US Patent:

7408253, Aug 5, 2008

Filed:

Mar 30, 2005

Appl. No.:

11/094111

Inventors:

Paul T. Lin - Dallas TX, US

International Classification:

H01L 23/02

US Classification:

257686, 257E23177, 257E23065, 361749, 361755, 174254

Abstract:

The present invention includes a chip-embedded support-frame wrapped-by-flex-circuit package assembly. The package assembly includes a flex circuit having a plurality of patterned connecting-traces. The package assembly further includes a plurality of semiconductor chips mounted on the flex circuits wherein the semiconductor chips having a plurality of contact terminals connected to corresponding connecting traces on the flex circuit. The package assembly further includes a support frame-board having an edge surface placed along predefined folded lines on the flex circuit. The frame-board has a plurality of open spaces for disposing each of the semiconductor chips therein. The flex circuit is provided for folding onto the support frame along the predefined folded lines to form the chip-embedded support-frame wrapped-by-flex-circuit package.

US Patent:

7667338, Feb 23, 2010

Filed:

Jul 23, 2007

Appl. No.:

11/880753

Inventors:

Paul T. Lin - Dallas TX, US
Chi-Shih Chang - Austin TX, US

International Classification:

H01L 23/28

US Classification:

257787, 257686

Abstract:

The present invention discloses an electronic package to contain and protect an integrated circuit (IC) chip. The electronic package further includes a leadframe, a flexible circuit or PCB type of substrate. The leadframe, flexible circuit or PCB type substrate further includes solder contacts, which are aligned with via holes in the molding layers on the top and bottom sides of the package. These via holes are for placing solder paste or solder balls from above and below for electrical access to the IC chip. These solder balls provide access for electrical testing after the package is mounted on a motherboard. They also provide the connection points for stacking multiple packages vertically.

US Patent:

20120020040, Jan 26, 2012

Filed:

Jul 26, 2011

Appl. No.:

13/136185

Inventors:

Paul T. Lin - Dallas TX, US
Michael B. McShane - Austin TX, US

International Classification:

H05K 1/18

US Classification:

361772

Abstract:

The present invention discloses the structure and process for fabrication of an electronic package to contain and protect Package-to-Package (P2P) stacked module of integrated circuit (IC) chips. The process includes a step of providing an interposer that includes conductive traces interconnected between pre-designated contact pads disposed on a top and/or bottom surfaces for mounting at least a top or bottom packages of the IC chips with electric terminals contacting the contact pads disposed on the top and/or bottom surface of the interposer. Standoffs and passive components can also be added onto interposer in order to improve solder joints reliability, electrical performance and main board density at the same time. The inclusion of passive components on the interposer could enhance the electrical performance and the testability of the finished package stack.