Paul J Logsdon

US Patent:

20210157963, May 27, 2021

Filed:

Nov 22, 2019

Appl. No.:

16/692129

Inventors:

- Armonk NY, US
Richard Frank Rizzolo - Red Hook NY, US
Bodo Hoppe - BOEBLINGEN, DE
Divya Kumudprakash Joshi - Hobli, IN
Paul Jacob Logsdon - Poughkeepsie NY, US
Sreekala Anandavally - Poughkeepsie NY, US
WILLIAM RURIK - Saint Paul MN, US

International Classification:

G06F 30/3312

Abstract:

A non-limiting example of a computer-implemented method for error injection includes executing a pre-silicon operation on a simulated chip verifying that a plurality of latches from a timing simulation set error checkers when run against a manufacturing test suite in order to generate a cross-reference file containing latch entries in a table. It executes a first post-silicon operation on a hardware chip based on the simulated chip to determine empirically that timing latches from logic built-in self tests (“LBIST”) trigger the same error checkers set by the plurality of latches verified in the simulated chip. The method updates the cross-reference file based on the results of the determination. The method executes a second post-silicon operation on the hardware chip to improve chip frequency by working around functional checkers using the cross-reference file and updating the cross-reference file based on the results of the improving.