Paul A Long

US Patent:

51104113, May 5, 1992

Filed:

Apr 27, 1990

Appl. No.:

7/516053

Inventors:

Paul Long - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2100

US Classification:

156656

Abstract:

Disclosed is a method of isotropically dry etching a WSi. sub. x /polysilicon sandwich structure on a silicon substrate wafer containing integrated semiconductor circuits. The method is conducted within a parallel plate reactor which in operation provides a substantially constant power density over the parallel plates. The reactor parallel plates are spaced a preselected separation distance from one another and a preselected amount of electrical power is applied thereto. Gases are injected to within the reactor provide a reactive gas mixture at a preselected pressure. The reactive gas mixture comprises SF. sub. 6, Cl. sub. 2, and O. sub. 2 in approximate respective volume ratios of 7. +-. 5%:5. +-. 5%:4. +-. 5%. The wafer is subjected to the reactive gas mixture at the preselected pressure for a preselected amount of time to selectively obtain a desired isotropic etch of the WSi. sub. x /polysilicon.

US Patent:

51604086, Nov 3, 1992

Filed:

Apr 27, 1990

Appl. No.:

7/516054

Inventors:

Paul Long - Meridian ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2100

US Classification:

156656

Abstract:

Disclosed is a method of isotropically dry etching a current conducting runner comprising polysilicon material which is formed on a silicon substrate wafer containing integrated semiconductor circuits. The method employs a parallel plate reactor which is controllable to provide intermittent pulses of power over the parallel plates. Gases are injected to within the reactor to provide a reactive gas mixture at a preselected pressure. Preselected intermittent pulses of power are applied to ionize the reactive gas mixture into a plasma state. Such intermittent pulses are defined by an RFon period, an RFoff period, and an RFrepeat period. The ratio of RFon:RFrepeat is preferably from about 0. 35 to 0. 60. The wafer is subjected to the intermittent pulses and reactive gas mixture at the preselected pressure for a preselected amount of time to selectively isotropically etch the current conducting runner. The invention has specific application to isotropically dry etching a WSi. sub.

US Patent:

50133985, May 7, 1991

Filed:

May 29, 1990

Appl. No.:

7/530139

Inventors:

Paul D. Long - Meridian ID
Jose J. Guerricabeitia - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21306
B44C 122
C03C 1500
C23F 102

US Classification:

156643

Abstract:

A plasma etch process to anisotropically etch a sandwich structure of silicon dioxide, polycrystalline silicon, and silicon dioxide "in situ", that is, in a single etch chamber. The silicon dioxide is etched using a SF. sub. 6 /CHF. sub. 3 /He chemistry. The polycrystalline silicon is etched using a HBr/He chemistry. A non-erodible cathode is used. Tungsten silicide may replace the polycrystalline silicon. Silicon nitride may replace the silicon dioxide.

US Patent:

20150162246, Jun 11, 2015

Filed:

Feb 19, 2015

Appl. No.:

14/626573

Inventors:

- Boise ID, US
Gordon Haller - Boise ID, US
Paul D. Long - Meridian ID, US

International Classification:

H01L 21/8234
H01L 27/115
H01L 29/66

Abstract:

Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.

US Patent:

20140239303, Aug 28, 2014

Filed:

Feb 22, 2013

Appl. No.:

13/774599

Inventors:

- Boise ID, US
Gordon Haller - Boise ID, US
Paul D. Long - Meridian ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/768
H01L 23/522

US Classification:

257 66, 438488

Abstract:

Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.