Paul A Mackey

US Patent:

7607031, Oct 20, 2009

Filed:

Jul 7, 2006

Appl. No.:

11/482269

Inventors:

Paul A. Mackey - Austin TX, US
Paul C. Miranda - Austin TX, US
Larry D. Hewitt - Austin TX, US
Jonathan M. Owen - Northborough MA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1/26

US Classification:

713300, 713310, 713323

Abstract:

A computer system includes a first and a second integrated circuit coupled by a communication link. The communication link operates in a power savings mode in which data is not transmitted over the link. Periodically, the communication link enters a training phase in which training patterns are transmitted over the communication link for a predetermined time period. The communication link returns to the power savings mode after the predetermined time period has elapsed. At least one sideband signal, separate from the communication link, and coupled between the first and second integrated circuits, is used to indicate when to enter the training phase from the power savings mode and exit the training phase and return to the power savings mode.

US Patent:

7617404, Nov 10, 2009

Filed:

Jul 7, 2006

Appl. No.:

11/482211

Inventors:

Paul A. Mackey - Austin TX, US
Paul C. Miranda - Austin TX, US
Larry D. Hewitt - Austin TX, US
Jonathan M. Owen - Northborough MA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1/26

US Classification:

713300, 713320, 713323

Abstract:

A first portion of a communication link is operated in a power savings mode at the same time that a second portion of the communication link is operated in a normal operational mode. For the first portion, a refresh mode is entered from the power savings mode in which one or more training patterns are transmitted over the first portion, while the second portion remains in the normal operational mode. An indication when to activate and deactivate the refresh mode may be sent over the second portion of the communication link. The refresh mode may be periodically entered from the power savings mode based on an interval register specifying the amount of time the communication link should remain in the power savings mode before a refresh occurs. In addition, the amount of time spent in the refresh mode may be programmable.

US Patent:

7856562, Dec 21, 2010

Filed:

May 2, 2007

Appl. No.:

11/743341

Inventors:

Alexander Branover - Brookline MA, US
Maurice Steinman - Marlborough MA, US
Frank Helms - Austin TX, US
Bill K. C. Kwan - Austin TX, US
W. Kurt Lewchuk - Austin TX, US
Paul Mackey - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1/26

US Classification:

713300, 713320

Abstract:

A method includes applying a voltage to a first processor core of a plurality of processor cores to deactivate the first processor core, the voltage less than a retention voltage of the first processor core. The application of the voltage can be in response to a software setting. The software setting can be configured via a user input, a software application, an operating system, or a BIOS setting. Alternately, the application of the voltage can be in response to a permanent hardware setting, such as the state of a fuse associated with the first processor core.

US Patent:

7870407, Jan 11, 2011

Filed:

May 18, 2007

Appl. No.:

11/750365

Inventors:

Alex Branover - Brookline MA, US
Frank P. Helms - Austin TX, US
Jonathan M. Owen - Northboro MA, US
Kurt Lewchuk - Austin TX, US
Maurice Steinman - Marlborough MA, US
Paul Mackey - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1/32

US Classification:

713323, 713300, 713310, 713320, 713330

Abstract:

A processor can operate in different power modes. In an active power mode, the processor executes software. In response to receiving a halt indication from the software, hardware at the processor evaluates bus transactions for the processor. If the bus transactions meet a heuristic, hardware places a processor core in a lower power mode, such as a retention mode. Because the bus transactions are evaluated by hardware, rather than by software, and the software is not required to perform handshakes and other protocols to place the processor in the lower power mode, the processor is able to place the processor core into the lower power mode more quickly, thereby conserving power.