Paul S Mackey

US Patent:

7856562, Dec 21, 2010

Filed:

May 2, 2007

Appl. No.:

11/743341

Inventors:

Alexander Branover - Brookline MA, US
Maurice Steinman - Marlborough MA, US
Frank Helms - Austin TX, US
Bill K. C. Kwan - Austin TX, US
W. Kurt Lewchuk - Austin TX, US
Paul Mackey - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1/26

US Classification:

713300, 713320

Abstract:

A method includes applying a voltage to a first processor core of a plurality of processor cores to deactivate the first processor core, the voltage less than a retention voltage of the first processor core. The application of the voltage can be in response to a software setting. The software setting can be configured via a user input, a software application, an operating system, or a BIOS setting. Alternately, the application of the voltage can be in response to a permanent hardware setting, such as the state of a fuse associated with the first processor core.

US Patent:

7870407, Jan 11, 2011

Filed:

May 18, 2007

Appl. No.:

11/750365

Inventors:

Alex Branover - Brookline MA, US
Frank P. Helms - Austin TX, US
Jonathan M. Owen - Northboro MA, US
Kurt Lewchuk - Austin TX, US
Maurice Steinman - Marlborough MA, US
Paul Mackey - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1/32

US Classification:

713323, 713300, 713310, 713320, 713330

Abstract:

A processor can operate in different power modes. In an active power mode, the processor executes software. In response to receiving a halt indication from the software, hardware at the processor evaluates bus transactions for the processor. If the bus transactions meet a heuristic, hardware places a processor core in a lower power mode, such as a retention mode. Because the bus transactions are evaluated by hardware, rather than by software, and the software is not required to perform handshakes and other protocols to place the processor in the lower power mode, the processor is able to place the processor core into the lower power mode more quickly, thereby conserving power.

US Patent:

20210327148, Oct 21, 2021

Filed:

Apr 9, 2021

Appl. No.:

17/226454

Inventors:

- New York NY, US
ANDREW GARRISON - NEW YORK NY, US
ADAM GREENBERG - NEW YORK NY, US
PAUL JOHNSON - NEW YORK NY, US
PAUL MACKEY - NEW YORK NY, US

Assignee:

JAND, Inc. - NEW YORK NY

International Classification:

G06T 19/00
G06F 3/0482
G06T 7/194
G06T 7/11
G06T 7/60
G06K 9/00
G06T 7/70
G06Q 30/06

Abstract:

A method for virtual try-on of user-wearable items is provided. The method includes capturing, in a client device, a first image of a user, the first image including a reference token for a user-wearable item and displaying, in the client device, images of multiple user-wearable items for the user, receiving an input from the user, the input indicative of a selected user-wearable item from the user-wearable items on display. The method also includes segmenting the first image to separate the reference token from a background comprising a portion of a physiognomy of the user, replacing a segment of the reference token in the first image with an image of the selected user-wearable item in a second image of the user, and displaying, in the client device, the second image of the user.