Paul R Martinez

US Patent:

57564000, May 26, 1998

Filed:

Dec 8, 1995

Appl. No.:

8/568064

Inventors:

Yan Ye - Campbell CA
Diana Xiaobing Ma - Saratoga CA
Gerald Zheyao Yin - Sunnyvale CA
Keshav Prasad - San Jose CA
Mark Siegel - Santa Clara CA
Paul Martinez - Milpitas CA
James S. Papanu - San Rafael CA
Danny Chien Lu - Milpitas CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23F 400
H01L 2100

US Classification:

438710

Abstract:

The present invention provides an apparatus and process for plasma cleaning the interior surfaces of semiconductor processing chambers. The method is directed to the dry etching of accumulated contaminant residues attached to the inner surfaces of the plasma processing chamber and includes introducing a cleaning gas mixture of a halogen-containing gas; activating a plasma in an environment substantially free of oxygen species; contacting the contaminant residues with the activated cleaning gas to volatilize the residues; and removing the gaseous by-products from the chamber. The etchant gaseous mixture comprises an even or greater amount of at least one fluorine-containing gas and an even or lesser amount of at least one chlorine-containing gas. The instant invention enables the intermittent use of the cleaning steps in an ongoing plasma processing of semiconductor wafers without chamber downtime and significant loss of wafer production.

US Patent:

20200178656, Jun 11, 2020

Filed:

Dec 5, 2018

Appl. No.:

16/211189

Inventors:

Paul Aurelio Martinez - Morgan Hill CA, US

International Classification:

A44C 13/00
A44C 5/00
A44C 5/18
A44C 15/00

Abstract:

A bracelet has a metal wrist piece in an arc of a user's wrist, T-bars implemented on opposite ends, each T-bar comprising a round bar of a length substantially the width of the body of the wrist piece, spaced apart from the body of the wrist piece by a T element, a first compound strap of flexible material with a through passage at one end in the direction of the width, a central slot opening into the passage, and a male snap element presented on a surface of the compound strap proximate an end of the strap opposite the through passage, and a second compound strap like the first but with a female snap element. The bars at the ends of the body of the wrist piece are inserted into the through passages through the slots into the through passages, joining the straps to the wrist piece on opposite sides.

US Patent:

20190096581, Mar 28, 2019

Filed:

Sep 27, 2017

Appl. No.:

15/717431

Inventors:

- Cupertino CA, US
Ming Y. Tsai - San Jose CA, US
Paul A. Martinez - Morgan Hill CA, US
Scott D. Morrison - Watertown MA, US
Tracey L. Chavers - Los Gatos CA, US

International Classification:

H01G 4/248
H01G 4/30
H01G 4/002
H01G 4/224
H05K 1/02
H05K 1/18

Abstract:

Capacitor devices with electrodes that are geometrically arranged to reduce parasitic capacitances are described. The capacitors may be multilayer ceramic capacitor (MLCC) structures in which certain electrodes may have a clearance from a capacitor structure wall, such as top wall. In circuits and devices where that particular capacitor wall may be placed near a shielding structure, the clearance may reduce unintended parasitic capacitances between the shield structure and the electrodes. As a result, the shield structures may be placed closer to the electronic components, which may allow circuit boards and electronic devices with a lower profile.

US Patent:

20190075655, Mar 7, 2019

Filed:

Nov 8, 2018

Appl. No.:

16/184697

Inventors:

- Cupertino CA, US
Paul A. Martinez - Morgan Hill CA, US

International Classification:

H05K 1/14
H05K 1/02
H05K 3/00
H05K 3/40
H05K 3/34
H05K 3/36
H05K 3/28
H05K 3/30
H05K 1/18
H05K 3/46

Abstract:

Methods and devices related to the design and fabrication of molded cores for printed circuit board assemblies and system-on-package (SIP) devices are discussed. The discussed printed circuit board assemblies may have multiple electrical components embedded in a molded core matrix and forming electrical connections with one or more printed circuit boards attached to the molded core matrix. Methods for sourcing of electrical components and production of the molded cores and printed circuit board assemblies are also discussed. The methods and devices may increase a volumetric density of electrical components in printed circuit board assemblies and provide improved mechanical properties to the electrical circuit device.

US Patent:

20180337003, Nov 22, 2018

Filed:

May 19, 2017

Appl. No.:

15/600329

Inventors:

- Cupertino CA, US
Albert Wang - Sunnyvale CA, US
Curtis C. Mead - Sacramento CA, US
Tyler S. Bushnell - San Francisco CA, US
Paul A. Martinez - Morgan Hill CA, US

International Classification:

H01G 4/35
H01G 4/12
H01G 4/005
H01G 4/30
H01L 41/047

Abstract:

Monolithic capacitor structures having a main capacitor and a vise capacitor are discussed. The vise capacitor provides to the monolithic capacitor structure reduced vibrations and/or acoustic noise due to piezoelectric effects. To that end, vise capacitor may cause piezoelectric deformations that compensate the deformations that are caused by the electrical signals in the main capacitor. Embodiments of these capacitor structures may have the main capacitor and the vise capacitor sharing portions of a rigid dielectric. Electrical circuitry that employs the vise capacitor to reduce noise and/or vibration in the monolithic capacitor structures is also described. Methods for fabrication of these capacitors are discussed as well.

US Patent:

20180092210, Mar 29, 2018

Filed:

Sep 23, 2016

Appl. No.:

15/274302

Inventors:

- Cupertino CA, US
Paul A. Martinez - Morgan Hill CA, US

International Classification:

H05K 1/14
H05K 1/18
H05K 1/02
H05K 3/30
H05K 3/28
H05K 3/36
H05K 3/34
H05K 3/40
H05K 3/00

Abstract:

Methods and devices related to the design and fabrication of molded cores for printed circuit board assemblies and system-on-package (SIP) devices are discussed. The discussed printed circuit board assemblies may have multiple electrical components embedded in a molded core matrix and forming electrical connections with one or more printed circuit boards attached to the molded core matrix. Methods for sourcing of electrical components and production of the molded cores and printed circuit board assemblies are also discussed. The methods and devices may increase a volumetric density of electrical components in printed circuit board assemblies and provide improved mechanical properties to the electrical circuit device.

US Patent:

20180061578, Mar 1, 2018

Filed:

Sep 1, 2017

Appl. No.:

15/694726

Inventors:

- Cupertino CA, US
Paul A. Martinez - Morgan Hill CA, US
Amanda R. Rainer - Sunnyvale CA, US
Won Seop Choi - Cupertino CA, US
Gemin Li - Pleasanton CA, US
Zhong-Qing Gong - Belmont CA, US
Shawn X. Arnold - Santa Cruz CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

H01G 4/30
H01G 4/008
H01G 4/232
H01G 4/12
H05K 1/18

Abstract:

Passive component structures that may save space, are readily manufactured, and are easy to use. In one example, a passive component structure may include two capacitors, each formed as a group of plates separate and apart from the other. The two groups of plates may have a spacing layer between them.

US Patent:

20170208710, Jul 20, 2017

Filed:

Jan 18, 2017

Appl. No.:

15/409260

Inventors:

- Cupertinio CA, US
Paul A. Martinez - Cupertino CA, US

International Classification:

H05K 9/00
H05K 3/30
G06F 1/16
G06F 1/26
H05K 1/18

Abstract:

The present disclosure relates to shield frames that reduce electromagnetic interference in electrical devices. The shield frames may be formed by coupling a shield frame lid to a ground connection of the circuit board through terminations in electrical components. The terminations in these electrical components thus may act both as a ground termination for the component as well as a ground connection for the shield frame. The components may be disposed in the perimeter of the circuit board to establish, with or without additional conductive posts, sections of the shield frame wall.