Paul F Murphy

US Patent:

6410916, Jun 25, 2002

Filed:

Aug 23, 1999

Appl. No.:

09/379644

Inventors:

Steven Jost - Amherst NH
Paul R. Murphy - Medford MA

Assignee:

BAE Systems Information and Electronic Systems Integration, Inc. - Nashua NH

International Classification:

G01J 500

US Classification:

250332, 250349

Abstract:

A high resolution room temperature infrared camera requires no cryogenic cooling and high vacuum packaging, normally though necessary for infrared target detection, by using a âblindâ polycrystalline lead salt resistor in combination with a matched active polycrystalline lead salt photoresistor both maintained at room temperature to provide a differential output indicative of an IR generating target. As a result of the matched components, the differential output nulls out the dark current which is the result of the ambient at the camera. The high degree of linearity associated with polycrystalline photoresistors permits fabrication of a differential detector where dark current in the active element is nulled out by equal and opposite current flow in a non-optically active reference resistor. Rather than a reference provided by a mechanical chopper normally used to correct for array non-uniformity, and rather than using costly temperature stabilization, the subject polycrystalline photoresistor provides a factory-setable reference, such that dark current can be canceled with the use of a nearly identical âblindâ element beside the optically active element.

US Patent:

6653642, Nov 25, 2003

Filed:

Feb 8, 2001

Appl. No.:

09/779243

Inventors:

Bjorn O. Pedersen - Chelmsford MA
Peter E. Maciejowski - Amesbury MA
William G. Goodenough - Exeter NH
Paul J. Murphy - Reading MA
Charles M. McKenna - Boxford MA

Assignee:

Varian Semiconductor Equipment Associates, Inc. - Gloucester MA

International Classification:

H01J 37317

US Classification:

25049221, 2504921, 315500, 315506, 315 541, 315 539

Abstract:

Methods and apparatus are provided for efficiently operating an ion implanter which includes a charged particle accelerator in a high energy mode and in a low energy mode. The charged particle accelerator includes a high voltage power supply, an accelerator column coupled to the high voltage power supply and a switching assembly. The accelerator column includes a plurality of accelerator electrodes. The high voltage power supply is disabled from energizing the accelerator column in the low energy mode. The switching assembly includes switching elements for electrically connecting the accelerator electrodes to a reference potential in the low energy mode and for electrically isolating the accelerator electrodes from the reference potential in the high energy mode. The switching assembly prevents positive potentials on the accelerator electrodes and thus minimizes space charge expansion of the beam when transporting positive ion beams in the low energy mode.

US Patent:

7394073, Jul 1, 2008

Filed:

Jan 20, 2006

Appl. No.:

11/336466

Inventors:

James J. Cummings - Wilmington MA, US
Joseph Olson - Beverly MA, US
Arthur H. Clough - Hardwick MA, US
Eric Hermanson - Georgetown MA, US
Rosario Mollica - Wilmington MA, US
Paul J. Murphy - Reading MA, US
Mark Donahue - Malden MA, US

Assignee:

Varian Semiconductor Equipment Associates, Inc. - Gloucester MA

International Classification:

G01K 1/08

US Classification:

250397, 25049221, 250396 R, 2504911, 2504921, 2504923

Abstract:

An angle measurement system for an ion beam includes a flag defining first and second features, wherein the second feature has a variable spacing from the first feature, a mechanism to translate the flag along a translation path so that the flag intercepts at least a portion of the ion beam, and a sensing device to detect the ion beam for different flag positions along the translation path and produce a sensor signal in response to the detected ion beam. The sensor signal and corresponding positions of the flag are representative of a vertical beam angle of the ion beam in a vertical plane. The sensing device may include a mask and a mechanism to translate the mask in order to define a beam current sensor on a portion of an associated Faraday sensor.

US Patent:

7727866, Jun 1, 2010

Filed:

Mar 4, 2009

Appl. No.:

12/397634

Inventors:

Nicholas Bateman - Burlington MA, US
Atul Gupta - Beverly MA, US
Paul Sullivan - Wenham MA, US
Paul Murphy - Reading MA, US

Assignee:

Varian Semiconductor Equipment Associates, Inc. - Gloucester MA

International Classification:

H01L 21/425

US Classification:

438514, 438 57, 438 73, 438455, 438458, 257617, 257E21568, 257E21346, 257E31032

Abstract:

The manufacture of solar cells is simplified and cost reduced through by performing successive ion implants, without an intervening thermal cycle. In addition to reducing process time, the use of chained ion implantations may also improve the performance of the solar cell. In another embodiment, two different species are successively implanted without breaking vacuum. In another embodiment, the substrate is implanted, then flipped such that it can be and implanted on both sides before being annealed. In yet another embodiment, one or more different masks are applied and successive implantations are performed without breaking the vacuum condition, thereby reducing the process time.

US Patent:

7888249, Feb 15, 2011

Filed:

Apr 14, 2010

Appl. No.:

12/760227

Inventors:

Nicholas P. T. Bateman - Reading MA, US
Atul Gupta - Beverly MA, US
Paul Sullivan - Wenham MA, US
Paul J. Murphy - Reading MA, US

Assignee:

Varian Semiconductor Equipment Associates, Inc. - Gloucester MA

International Classification:

H01L 21/425

US Classification:

438527, 438 57, 438514, 438530, 257617, 257E21346, 257E21135, 257E31032

Abstract:

The manufacture of solar cells is simplified and cost reduced through by performing successive ion implants, without an intervening thermal cycle. In addition to reducing process time, the use of chained ion implantations may also improve the performance of the solar cell. In another embodiment, two different species are successively implanted without breaking vacuum. In another embodiment, the substrate is implanted, then flipped such that it can be and implanted on both sides before being annealed. In yet another embodiment, one or more different masks are applied and successive implantations are performed without breaking the vacuum condition, thereby reducing the process time.

US Patent:

7935942, May 3, 2011

Filed:

Aug 15, 2006

Appl. No.:

11/504367

Inventors:

Jonathan England - Horsham, GB
Steven R. Walther - Andover MA, US
Richard S. Muka - Topsfield MA, US
Julian Blake - Gloucester MA, US
Paul J. Murphy - Reading MA, US
Reuel B. Liebert - Peabody MA, US

Assignee:

Varian Semiconductor Equipment Associates, Inc. - Gloucester MA

International Classification:

H01J 37/00

US Classification:

25049221, 2504921, 2504922, 2504923, 2504431, 118723 CB, 118723 FI

Abstract:

A technique for low-temperature ion implantation is disclosed. In one particular exemplary embodiment, the technique may be realized as an apparatus for low-temperature ion implantation. The apparatus may comprise a pre-chill station located in proximity to an end station in an ion implanter. The apparatus may also comprise a cooling mechanism within the pre-chill station. The apparatus may further comprise a loading assembly coupled to the pre-chill station and the end station. The apparatus may additionally comprise a controller in communication with the loading assembly and the cooling mechanism to coordinate loading a wafer into the pre-chill station, cooling the wafer down to a predetermined temperature range, and loading the cooled wafer into the end station where the cooled wafer undergoes an ion implantation process.

US Patent:

8319196, Nov 27, 2012

Filed:

May 2, 2011

Appl. No.:

13/099203

Inventors:

Jonathan G. England - Horsham, GB
Steven R. Walther - Andover MA, US
Richard S. Muka - Topsfield MA, US
Julian G. Blake - Gloucester MA, US
Paul J. Murphy - Reading MA, US
Reuel B. Liebert - Peabody MA, US

Assignee:

Varian Semiconductor Equipment Associates, Inc. - Glouscester MA

International Classification:

H01J 37/00

US Classification:

25049221, 2504921, 2504922, 2504923, 2504431, 118723 CB, 118723 FI

Abstract:

A technique for low-temperature ion implantation is disclosed. In one particular exemplary embodiment, the technique may be realized as an apparatus for low-temperature ion implantation. The apparatus may comprise a pre-chill station located in proximity to an end station in an ion implanter; a cooling mechanism within the pre-chill station configured to cool a wafer from ambient temperature to a predetermined range less than ambient temperature; a loading assembly coupled to the pre-chill station and the end station; and a controller in communication with the loading assembly and the cooling mechanism to coordinate loading a wafer into the pre-chill station, cooling the wafer down to the predetermined temperature range before any ion implantation into the wafer, and loading the cooled wafer into the end station where the cooled wafer undergoes an ion implantation process.

US Patent:

8467158, Jun 18, 2013

Filed:

Jun 18, 2010

Appl. No.:

12/818454

Inventors:

Kasegn D. Tekletsadik - Middleton MA, US
Roger B. Fish - Bedford MA, US
Paul J. Murphy - Reading MA, US

Assignee:

Varian Semiconductor Equipment Associates, Inc. - Gloucester MA

International Classification:

H02H 3/00

US Classification:

361 19, 361 62

Abstract:

A new type of superconducting fault current limiter is disclosed, which can advantageously be used with high voltage transmission networks. The circuit is electrically connected to two terminals, which connect to the transmission network. The superconducting circuit is located within an enclosure or tank, which is electrically isolated from ground. Therefore, the voltage difference between the enclosure and the superconducting circuit, and between the enclosure and the terminals are significantly less than exist in current deployments. In some embodiments, the enclosure is electrically connected to one of the terminals, while in other embodiments, the enclosure is electrically isolated from the terminals. The circuit can be combined with other like circuits to address a wide range of current transmission network configurations.