Paul L Peirson

US Patent:

49892100, Jan 29, 1991

Filed:

Mar 19, 1990

Appl. No.:

7/499231

Inventors:

James H. Scheuneman - St. Paul MN
Paul L. Peirson - Forest Lake MN
Michael E. Mayer - Fridley MN

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 1110

US Classification:

371 401

Abstract:

A memory system which is shared by a plurality of requestors each of which supply read and write address bits to the memory system is read out of, or written into, in accordance with read and write address bits. A sequencer is utilized to initiate a sequence of timing signals that control the reading, writing and partial writing of data. Certain ones of these signals occur at fixed intervals from the receipt of an initial load address signal. A read address circuit coupled to receive the read address bits generates a set of check bits. A read address stack means stores each set of read address check bits upon the occurrence of an associated load read address stack signal. A write address check bit generator means is coupled to receive write address bits and to generate a set of check bits representative of the write address bits. A write address stack means stores each set of the write address check bits upon the occurrence of an associated load write address stack signal. A read address stack selector and a write address stack selector read out read address check bits and write address check bits, while the sequencer controls the transmission of the read address check bits and the write address check bits to an error detection circuit.

US Patent:

49186957, Apr 17, 1990

Filed:

Aug 30, 1988

Appl. No.:

7/238083

Inventors:

James H. Scheuneman - St. Paul MN
Michael E. Mayer - Fridley MN
Paul L. Peirson - Forest Lake MN

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 1110

US Classification:

371 511

Abstract:

A failure detection system for variable field partial write system for merging data bits in a memory word upon programmable request is described. The variable bit field can be selected for any number of bit positions from a single bit up to and including a full data word, where data words are comprised of a predetermined number of bytes each containing a predetermined number of bits. A Start Bit Code defines the location of the start of the bit field to be written and an End Bit Code defines the bit after the last bit that is to be merged and written. Write and Read Data to be used in the partial merge operation are stored in a Merge Register along with a code derived from the Start and End Code bits. The bits not used are stored in a Non-Merge Register. Parities are compared to verify that a parity error did not occur when the Merge Register was loaded.