Paul J Price

US Patent:

6678875, Jan 13, 2004

Filed:

Dec 20, 2002

Appl. No.:

10/323979

Inventors:

Brian John Pajak - Millbury MA
Paul Price - Stoughton MA
Jean-François Côté - Chelsea, CA
Luc Romain - Aylmer, CA

Assignee:

LogicVision, Inc. - San Jose CA

International Classification:

G06F 1750

US Classification:

716 11, 716 2, 716 3, 716 5, 716 8, 716 17

Abstract:

An embedded test, chip design utility is an ease-of-use utility for assisting a circuit designer in quickly implementing a circuit embedded test design flow. Using the utility, a designer transforms a design netlist to include embedded test structures. The utility automatically builds a workspace containing a predetermined repository structure and design environment, generates control files for executing design automation tools that operate within the design flow, and encapsulates the data so as to be self-contained and easily transferable to other design teams.

US Patent:

6725435, Apr 20, 2004

Filed:

Dec 20, 2002

Appl. No.:

10/323815

Inventors:

Jean-François Côté - Chelsea, CA
Paul Price - Stoughton MA

Assignee:

LogicVision, Inc. - San Jose

International Classification:

G06F 1750

US Classification:

716 5, 4 6

Abstract:

A sign-off method for use in verifying of embedded test structures in a circuit design extracts a description of all embedded test structures from a circuit description to create a test connection map file, and verifies the connections of the test structures to circuit pins or nets, creates verification configuration files for use, in performing a sign-off verification of the circuit, for a circuit containing logic test structures, verifies that each logic test structure complies with logic test design rules and creates logic test vectors and a reference signature, performs a formal verification and a static timing analysis of the circuit, generates a sign-off simulation test bench for each test structure using the verification configuration files and the test connection map file, executes the test benches to simulate all test structures in the circuit; and creates manufacturing test patterns.

US Patent:

7103860, Sep 5, 2006

Filed:

Jan 23, 2003

Appl. No.:

10/349452

Inventors:

Paul Price - Stoughton MA, US
Jean-François Côté - Chelsea, CA
Ajit Kumar Verma - San Jose CA, US

Assignee:

LogicVision, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 4, 716 5, 702117, 703 20

Abstract:

A program product for use in generating test benches for verifying test structures embedded in a circuit, comprises a verification specification processor for parsing a verification specification containing test specifications for selected test structures and a test bench generator for each of one or more types of embedded test structures, each test bench generator being operable to process a test structure specification of a test structure of a corresponding test structure type and generate a test bench using data contained in said test specifications of said verification specification, data contained in said test structure specification and data contained in a test connection specification.

US Patent:

20050240848, Oct 27, 2005

Filed:

Apr 20, 2005

Appl. No.:

11/109844

Inventors:

Jean-Francois Cote - Chelsea, CA
Paul Price - Stoughton MA, US
Benoit Nadeau-Dostie - Gatineau, CA

Assignee:

LogicVision, Inc. - San Jose CA

International Classification:

G01R031/28

US Classification:

714726000

Abstract:

A masking circuit for selectively masking scan chain inputs and/or outputs during scan testing of an integrated circuit, comprises a mask register having at least two mask register elements for each scan chain to provide a plurality of masking modes; and an input and output mask control circuit for each scan chain, each mask control circuit being connected between a test pattern source and a signature register and between a serial input and a serial output of an associated scan chain and being responsive to mask control data stored in the register elements for configuring the associated scan chain in one of the plurality of masking modes during a scan test of the circuit.