Paul M Schanely

US Patent:

6525738, Feb 25, 2003

Filed:

Jul 16, 1999

Appl. No.:

09/356230

Inventors:

Robert J. Devins - Essex Junction VT
Robert S. Horton - Colchester VT
Paul M. Schanely - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G09G 536

US Classification:

345553, 345502, 345559, 345558, 345565

Abstract:

A system and method for decoupling graphics operations from a host processor to improve the efficiency of graphics rendering and free the host processor for other essential tasks. A processing system includes a host processor, a memory, a display list processor (DLP), graphics accelerators and display hardware. The host processor builds display lists generated by graphics applications and stores the display lists in the memory. The display lists include hardware function directives and control directives. The DLP accesses the memory to process the display lists, issuing the hardware function directives to the accelerators to generate display data.

US Patent:

6762761, Jul 13, 2004

Filed:

Mar 31, 1999

Appl. No.:

09/283387

Inventors:

Robert J. Devins - Essex Junction VT
Paul M. Schanely - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1516

US Classification:

345503, 345522, 345545, 345553

Abstract:

A computer-implemented method and system for performing graphics rendering on demand on a graphics subsystem, with only nominal host system operations being required. High-level specifications of graphics operations in a computer program are captured as I/O hardware programs in a memory. A graphics processor in the subsystem issues instructions in the captured programs to a graphics accelerator, which executes the instructions to perform graphics operations. The graphics accelerator has a status indicator containing status information relating to hardware events incident to the graphics operations. Under the control of instructions in the captured program, the graphics processor monitors the status indicator, and either issues, or delays issuing, the instructions in the captured programs, depending upon the status information in the indicator.

US Patent:

6952215, Oct 4, 2005

Filed:

Mar 31, 1999

Appl. No.:

09/283386

Inventors:

Robert J. Devins - Essex Junction VT, US
Paul M. Schanely - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06T015/00

US Classification:

345522, 345503, 345553, 719323, 719328

Abstract:

A computer-implemented method and system for performing graphics rendering on demand on a graphics subsystem, with only nominal host system operations being required. An application program requiring graphics to be rendered is coded to bound a sequence of calls to basic rendering functions, defining a desired image to be rendered, between begin-program and end-program identifiers. When the application program is executed on a host operating system, a begin-program identifier invokes a function in a graphics device driver in the host system. The function captures the calls to the rendering functions within the application program in a memory as hardware instructions to the graphics subsystem. When the function encounters an end-program identifier, it registers the captured hardware instructions with the host system as an executable program. Subsequently, the application may render the image upon demand by calling the registered executable program, which will execute from the memory on the graphics subsystem, with only nomimal host processor operations being required.

US Patent:

7065602, Jun 20, 2006

Filed:

Jul 1, 2003

Appl. No.:

10/604205

Inventors:

Robert S. Horton - Colchester VT, US
David W. Milton - Underhill VT, US
Clarence R. Ogilvie - Huntington VT, US
Paul M. Schanely - Essex Junction VT, US
Sebastian T. Ventrone - South Burlington VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/14

US Classification:

710305, 710105

Abstract:

The invention transmits data on an integrated circuit chip by first propagating a first data portion along a first segment of a segmented data line and then propagating the first data portion along a second segment of the segmented data line and simultaneously propagating a second data portion along the first segment of the segmented data line. The invention breaks a single data transmission into such different data portions and later reassembles the different data portions back into the single data transmission after all of the different data portions have been individually transmitted along all portions of the segmented data line.

US Patent:

7176927, Feb 13, 2007

Filed:

Sep 22, 2003

Appl. No.:

10/665289

Inventors:

Robert J. Devins - Essex Junction VT, US
Paul M. Schanely - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/16
G06F 15/00
G09G 5/36

US Classification:

345503, 345501, 345553

Abstract:

A computer-implemented method and system for performing graphics rendering on demand on a graphics subsystem, with only nominal host system operations being required. High-level specifications of graphics operations in a computer program are captured as I/O hardware programs in a memory. A graphics processor in the subsystem issues instructions in the captured programs to a graphics accelerator, which executes the instructions to perform graphics operations. The graphics accelerator has a status indicator containing status information relating to hardware events incident to the graphics operations. Under the control of instructions in the captured program, the graphics processor monitors the status indicator, and either issues, or delays issuing, the instructions in the captured programs, depending upon the status information in the indicator.

US Patent:

7480888, Jan 20, 2009

Filed:

May 21, 2008

Appl. No.:

12/124771

Inventors:

Clarence Rosser Ogilvie - Huntington VT, US
Charles B. Winn - Colchester VT, US
David Wills Milton - Underhill VT, US
Kenneth Anthony Lauricella - Colchester VT, US
Nitin Sharma - South Burlington VT, US
Paul Mark Schanely - Essex Junction VT, US
Robert Dov Herzl - South Burlington VT, US
Robert Spencer Horton - Colchester VT, US
Tad Jeffrey Wilder - South Hero VT, US
Douglas P. Nadeau - Underhill VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 14, 716 1, 716 18, 716 19

Abstract:

A design structure embodied in a machine-readable medium is disclosed in one embodiment of the invention as including a flexible logic block to facilitate engineering changes at selected locations within an IC. The flexible logic block has a consistent and identifiable structure such that a simple automated process may be used to reconfigure the structure to perform different logical operations. In certain embodiments, the flexible logic block includes a circuit, such as a multiplexer, having multiple inputs and at least one output. A metal interconnect structure is coupled to the inputs and enables connection of each of the inputs to one of several electrical potentials using a focused-ion-beam (FIB) tool. In this way, the circuit may be configured to perform different logical operations after components in the IC exist in hardware.

US Patent:

7536496, May 19, 2009

Filed:

Feb 28, 2006

Appl. No.:

11/276449

Inventors:

W. Riyon Harding - Richmond VT, US
David W. Milton - Underhill VT, US
Clarence Rosser Ogilvie - Huntington VT, US
Jason E. Rotella - Mineville NY, US
Paul M. Schanely - Essex Junction VT, US
Sebastian T. Ventrone - South Burlington VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/00
G06F 13/42
G06F 13/362
H04L 12/28
H04L 12/56
H03K 17/00

US Classification:

710316, 710106, 710113, 370389, 340 21

Abstract:

A method and apparatus for transmitting data between cores residing in an integrated circuit. Data is transmitted by using hubs located between the cores and an arbiter. The arbiter maintains a table that contains all the valid combinations of routing paths between the cores.

US Patent:

8060845, Nov 15, 2011

Filed:

Jul 15, 2008

Appl. No.:

12/173222

Inventors:

Robert D. Herzl - South Burlington VT, US
Robert S. Horton - Colchester VT, US
Kenneth A. Lauricella - Colchester VT, US
David W. Milton - Underhill VT, US
Clarence R. Ogilvie - Huntington VT, US
Paul M. Schanely - Essex Junction VT, US
Nitin Sharma - South Burlington VT, US
Tad J. Wilder - South Hero VT, US
Charles B. Winn - Colchester VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716103, 716104, 716132

Abstract:

A method is provided for updating an existing netlist to reflect a design change. A register transfer level (RTL) design incorporating the design change and the existing netlist are provided to a synthesis tool. The existing netlist is set to a read-only condition to prevent a change to the existing netlist. The design and the read-only existing netlist are processed with the synthesis tool reusing logic structures from the read-only existing netlist by performing an optimization of the design and the read-only existing netlist with an objective to minimize the design space. The optimization is constrained by the read-only existing netlist. A result is generated by the synthesis tool including the existing netlist and a new portion of a netlist reflecting the design change.