Paul J Schumacher

US Patent:

7133978, Nov 7, 2006

Filed:

Jun 19, 2003

Appl. No.:

10/600851

Inventors:

Philip B. James-Roxby - Longmont CO, US
Charles A. Ross - Fort Collins CO, US
Paul R. Schumacher - Rochester MN, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 12/14

US Classification:

711152, 711164

Abstract:

Method and apparatus for processing data stored in a memory shared among a plurality of processors is described. In an example, a semaphore is provided that is associated with a first portion of the memory. Tasks are stored in the first portion of the memory, the tasks being respectively related to data segments stored in a second portion of the memory. A state of the semaphore is determined. Access among the plurality of processors to the first portion of the memory is controlled in response to the state of the semaphore. A task is executed to process a data segment of the data segments in response to a processor of the plurality of processors gaining access to the first portion of the memory.

US Patent:

7380232, May 27, 2008

Filed:

Mar 10, 2006

Appl. No.:

11/373709

Inventors:

Paul R. Schumacher - Berthoud CO, US
Jorn W. Janneck - San Jose CA, US
David B. Parlour - Fox Chapel PA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 18, 716 16, 716 17

Abstract:

Method and apparatus for designing a system for implementation in a programmable logic device (PLD) is described. In one example, a program language description of the system is captured. The program language description includes control code for configuring actor elements with functions to perform tasks in response to input data. A hardware implementation is generated for the PLD from the program language description by mapping the control code to decision logic, the functions to partial configuration streams, and the actor elements to reconfigurable slots.

US Patent:

7385532, Jun 10, 2008

Filed:

Feb 16, 2007

Appl. No.:

11/707616

Inventors:

Paul R. Schumacher - Berthoud CO, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03M 7/38
H03M 7/34

US Classification:

341 51, 341106, 341 1

Abstract:

An extended bitstream, and generation thereof, for dynamically configuring a decoder. Content data is obtained to be encoded. Build settings are obtained for configuring the decoder. The content data is encoded with an encoder to provide encoded data. A configuration bitstream is generated for configuring programmable logic responsive to the build settings. The configuration bitstream is combined with the encoded data to provide the extended bitstream. The extended bitstream is self-contained to allow for configuring of the programmable logic to dynamically instantiate the decoder to decode the encoded data.

US Patent:

7519823, Apr 14, 2009

Filed:

Aug 12, 2004

Appl. No.:

10/917042

Inventors:

Paul R. Schumacher - Berthoud CO, US
Robert D. Turney - Watertown WI, US
Mark Paluszkiewicz - Schaumburg IL, US
Prasanna Sundararajan - Mountain View CA, US
Brandon J. Blodget - Santa Clara CA, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

H04L 9/00

US Classification:

713176, 713 1, 713 2, 713100, 713168, 713189, 380268, 716 16, 716 17, 716 18

Abstract:

Various approaches for embedding identifier information in a configuration bitstream for a programmable logic device (PLD) are disclosed. In various embodiments, the bits in the configuration bitstream that are unused in implementing a the design are identified. The identifier information is encrypted, and a subset of the unused bits are selected using a pseudo-random function. The encrypted identifier information is placed in the selected subset of unused bits. Decryption is accomplished by reversing the encryption approach.

US Patent:

7669037, Feb 23, 2010

Filed:

Mar 10, 2005

Appl. No.:

11/076797

Inventors:

Paul R. Schumacher - Berthoud CO, US
Kornelis Antonius Vissers - Sunnyvale CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 15/76

US Classification:

712 34, 712 35

Abstract:

Method and apparatus for communication between hardware blocks and a processor in a programmable logic device is described. A shared memory is provided along with a memory controller for controlling access to the shared memory. An interface is configured to receive auxiliary instructions from the processor, select the hardware blocks for the requested tasks in response to the auxiliary instructions, notify the hardware blocks of those tasks, and arbitrate access to the memory controller among the hardware blocks.

US Patent:

7684278, Mar 23, 2010

Filed:

Aug 26, 2008

Appl. No.:

12/198733

Inventors:

Paul R. Schumacher - Berthoud CO, US
Mark Paluszkiewicz - Schaumburg IL, US
Kornelis A. Vissers - Sunnyvale CA, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

G11C 8/00

US Classification:

36523002, 36523003, 36523005, 326 38, 326 41, 326 46, 326 47, 711147, 711202

Abstract:

Method and apparatus for implementing first-in-first-out (FIFO) memories using time-multiplexed memory in an integrated circuit are described. A block random access memory (BRAM) circuit embedded in the integrated circuit is provided. The BRAM includes at least one port responsive to a respective at least one BRAM clock signal. FIFO logic is configured to implement a plurality of FIFOs in the BRAM having a plurality of interfaces. Multiplexer logic is configured to selectively couple the plurality of output interfaces of the FIFO logic to the at least one port of the BRAM circuit responsive to at least one FIFO clock signal. Each of the at least one BRAM clock signal has at least twice the frequency of a respective one of the at least one FIFO clock signal.

US Patent:

7881320, Feb 1, 2011

Filed:

Dec 12, 2005

Appl. No.:

11/299854

Inventors:

Paul R. Schumacher - Berthoud CO, US
Kornelis Antonius Vissers - Sunnyvale CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H04L 12/50
H04L 12/28
G06F 13/00
G06F 9/26

US Classification:

370412, 370383, 370419, 711137, 711204, 711213

Abstract:

Multiplexing data from bitstreams is described. Data status is determined for data of each of the bitstreams. Stream numbers are assigned respectively to the bitstreams, and the data of each of the bitstreams is controllably stored in respective memory. A memory buffer of the memory buffers is controllably selected. The data obtained from the memory buffer selected is parsed to provide an output. The controllably selecting and the parsing are repeated to obtain and parse the data stored in at least one other memory buffer of the memory buffers to provide the output. The output is multiplexed data from the bitstreams respectively associated with the memory buffer and the at least one other memory buffer.

US Patent:

7917876, Mar 29, 2011

Filed:

Mar 27, 2007

Appl. No.:

11/729206

Inventors:

Paul R. Schumacher - Berthoud CO, US
Daniel L McMurtrey - Albuquerque NM, US
Shengqi Yang - Chandler AZ, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716116, 716117

Abstract:

Method and apparatus for designing an embedded system for a programmable logic device (PLD) is described. Parameters specific to the embedded system are obtained. Source code files that use the parameters to define configurable attributes of the base platform are generated. A software definition and a hardware definition are obtained. The software and hardware definitions each use an application programming interface (API) of the base platform to define communication between software and hardware of the embedded system. An implementation of the embedded system is automatically built for the PLD using the source code files, the software definition, and the hardware definition.