Paul Jerome Short

US Patent:

7406550, Jul 29, 2008

Filed:

Jan 11, 2006

Appl. No.:

11/329906

Inventors:

Paul Jerome Short - Albuquerque NM, US
William Broome - Albuquerque NM, US
Taylor Wray - Albuquerque NM, US
Andrew David Alsup - Albuquerque NM, US

Assignee:

Innovasic, Inc - Albuquerque NM

International Classification:

G06F 13/12

US Classification:

710 62, 710 8, 710 11, 710 63, 710 72, 718102, 718103, 718108

Abstract:

A deterministic microcontroller includes a plurality of blocks of cache memories formed on the same integrated circuit as the microprocessor unit. A corresponding plurality of hardware contexts for the microcontroller is provided by the plurality of sets of hardware registers. A context manager controls the selection of the hardware registers such that contexts are changed within one bus cycle and a plurality of hardware contexts are provided. The deterministic microcontroller includes a configurable input/output interface that is programmable to handle any one of a plurality of interfaces that embedded applications might have, including communication protocols and bus interfaces, data acquisition from multiple sensors and actuators, and controls of various motors.

US Patent:

7479802, Jan 20, 2009

Filed:

Dec 22, 2007

Appl. No.:

12/004767

Inventors:

Dean J. Arriens - Tijeras NM, US
Paul Short - Albuquerque NM, US

Assignee:

Quadric, Inc - Albuquerque NM

International Classification:

H03K 19/173

US Classification:

326 38, 326 47, 708232

Abstract:

A programmable integrated circuit for calculating a digital algorithm is disclosed. The integrated circuit is programmable to operate on input data in accordance with one or more predetermined digital algorithms.

US Patent:

7526579, Apr 28, 2009

Filed:

Jan 3, 2006

Appl. No.:

11/324541

Inventors:

Taylor Wray - Albuquerque NM, US
Paul Jerome Short - Albuquerque NM, US
William Broome - Albuquerque NM, US

Assignee:

Innovasic, Inc. - Albuquerque NM

International Classification:

G06F 3/00

US Classification:

710 11, 710 8, 710 62, 710 63, 710 72, 718102, 718103, 718108

Abstract:

A configurable input/output interface is described that can be programmed to handle any one of a plurality of interfaces that embedded applications might have, including communication protocols and bus interfaces, data acquisition from multiple sensors and actuators, and controls of various motors.

US Patent:

7680967, Mar 16, 2010

Filed:

Jan 3, 2006

Appl. No.:

11/324388

Inventors:

William Broome - Albuquerque NM, US
Paul Jerome Short - Albuquerque NM, US
Taylor Wray - Albuquerque NM, US

Assignee:

Innovasic, Inc. - Albuquerque NM

International Classification:

G06F 13/12
G06F 7/38

US Classification:

710 62, 326 37, 326 38, 326 39, 326 41

Abstract:

A configurable application specific product with a configurable input/output interface is described. The illustrative embodiment of the invention includes a single microcontroller and a microprocessor having a configurable I/O interface that can be programmed to handle any one of a plurality of interfaces that embedded applications might have, including communication protocols and bus interfaces, data acquisition from multiple sensors and actuators, and controls of various motors.

US Patent:

7843215, Nov 30, 2010

Filed:

Dec 22, 2007

Appl. No.:

12/004766

Inventors:

Dean J. Arriens - Tijeras NM, US
Paul Short - Albuquerque NM, US

Assignee:

Quadric, Inc. - Albuquerque NM

International Classification:

H03K 19/173

US Classification:

326 38

Abstract:

An integrated circuit comprising a reconfigurable arrangement to compute digital algorithms by operating on digital data is provided on an integrated circuit. The integrated circuit includes a plurality of data inputs, a plurality of data outputs, a plurality of programming inputs and a plurality of logic units arranged as a matrix array. At least some of the logic units each comprise a Boolean logic computational unit having input terminals, output terminals, and programming terminals. The logic units are operated on a clocked basis such that each logic unit is controlled by the programming inputs. Each logic unit comprises a selector coupled to the input terminals and programmable to selectively couple input data from either the data inputs or output terminals of one or more other computational units to the computational unit. An array of programmable interconnects the data inputs of the matrix array and the output terminals of each of the logic units with input terminals of other logic units and to the data outputs of the matrix array. Each of the logic units and each of the selectors and the array of programmable interconnects are operated on a clocked basis such that Boolean functionality is determined during each clock cycle.

US Patent:

20070240093, Oct 11, 2007

Filed:

Apr 10, 2007

Appl. No.:

11/787206

Inventors:

Paul Short - Albuquerque NM, US

Assignee:

Quadric, Inc. - Albuquerque NM

International Classification:

G06F 17/50
H03K 19/00

US Classification:

716017000

Abstract:

A customizable integrated circuit is programmed to provide both hardware task functions and interconnects. A plurality of execution units is executable concurrently to emulate hardware tasks. A plurality of programmable locations provides logical interconnect between the executable programs.

US Patent:

49411160, Jul 10, 1990

Filed:

Jul 15, 1988

Appl. No.:

7/220052

Inventors:

William R. Hancock - Cedar Crest NM
Paul J. Short - Albuquerque NM
Thomas A. Weingartner - Albuquerque NM

Assignee:

Honeywell Inc. - Minneapolis MN

International Classification:

G06F 102

US Classification:

364718

Abstract:

A symbol generator useful for stroke based and raster display systems provides the ability of generating ellipses and elliptical arc segments. A look-up table provides cosine and sine values for incremental angles which are multiplied by major and minor axis scale factors for a selected ellipse. Global input parameters permit rotation of all arcs and vectors to generate orthogonal projections, thereby producing 2-D and 3-D symbology.

US Patent:

62976664, Oct 2, 2001

Filed:

Nov 23, 1999

Appl. No.:

9/447525

Inventors:

Thomas A. Weingartner - Albuquerque NM
Paul J. Short - Albuquerque NM
Mark A. Espelien - Albuquerque NM
Jordon W. Woods - Albuquerque NM

Assignee:

InnoVasic, Inc. - Albuquerque NM

International Classification:

H01L 2500

US Classification:

326 41

Abstract:

A method and apparatus for a fully programmable and configurable application specific integrated circuit (FPCA). Programmable I/O cells are programmed for selected electrical characteristics, including power and ground. The circuit contains a functional core for programming the circuit, programmable I/O leads to connect to the programmable I/O cells, and programming logic and control for programming the functional core and I/O cells. Certain leads double as programmable I/O leads and programming control leads, and are used to communicate with the programming logic and control and the I/O cells. A method of programming the FPCA comprises the steps of asserting the programming control signal; applying programming voltage and ground to a respective two designated I/O cells' leads; isolating a plurality of the I/O cells from the programming signal; and programming an FPGA array in addition to the isolated I/O cells of the circuit.