Paul R Stonelake

US Patent:

7340576, Mar 4, 2008

Filed:

Jul 28, 2004

Appl. No.:

10/901010

Inventors:

Christophe Therene - Livermore CA, US
Paul R. Stonelake - Santa Clara CA, US
Alex Ga Hing Tang - Fremont CA, US
Richard L. Harris - San Jose CA, US

Assignee:

Applied Micro Circuits Corporation - San Diego CA

International Classification:

G06F 12/00

US Classification:

711164, 711114, 711152, 711112, 711113

Abstract:

A disk array controller reliably detects disk drive power-on-reset events that may cause a disk drive that has uncommitted write data stored in its cache to lose such data. The methods for detecting the power-on-reset events include operating the disk drives in an ATA security mode in which a power-on-reset of a disk drive will cause the drive to enter a locked state in which data transfer commands are aborted; and tracking power cycle count attributes of the disk drives over time. When a disk drive power-on-reset event is detected, the disk array may be efficiently maintained in an operational state by re-executing or “replaying” a set of write commands that are cached within the disk array controller. The invention is also applicable to single-disk-drive storage systems.

US Patent:

7590875, Sep 15, 2009

Filed:

Jan 22, 2007

Appl. No.:

11/625555

Inventors:

Christophe Therene - Livermore CA, US
Paul R. Stonelake - Santa Clara CA, US
Alex Ga Hing Tang - Fremont CA, US
Richard L. Harris - San Jose CA, US

Assignee:

Applied Micro Circuits Corporation - San Diego CA

International Classification:

G06F 12/00

US Classification:

713300, 711112, 711113, 711114, 711152, 711164

Abstract:

A disk array controller reliably detects disk drive power-on-reset events that may cause a disk drive that has uncommitted write data stored in its cache to lose such data. The methods for detecting the power-on-reset events include operating the disk drives in an ATA security mode in which a power-on-reset of a disk drive will cause the drive to enter a locked state in which data transfer commands are aborted; and tracking power cycle count attributes of the disk drives over time. When a disk drive power-on-reset event is detected, the disk array may be efficiently restored to an operational state by re-executing or “replaying” a set of write commands that are cached within the disk array controller. The invention is also applicable to single-disk-drive storage systems.

US Patent:

8458495, Jun 4, 2013

Filed:

Aug 5, 2009

Appl. No.:

12/536405

Inventors:

Christophe Therene - Livermore CA, US
Paul R. Stonelake - Santa Clara CA, US
Alex Ga Hing Tang - Fremont CA, US
Richard L. Harris - San Jose CA, US

Assignee:

Summit Data Systems LLC - Frisco TX

International Classification:

G06F 12/00

US Classification:

713300, 713310, 713320, 713321, 713322, 713323, 713324, 713330, 713340, 711112, 711113, 711114

Abstract:

A disk array controller detects disk drive power-on-reset events that may cause a disk drive to lose uncommitted write data stored in its cache. When an unexpected disk drive power-on-reset event is detected, the disk array controller may initiate an appropriate corrective action. For example, the disk array controller may initiate a disk drive rebuild operation, or may re-send a set of write commands to the disk drive.

US Patent:

20120324148, Dec 20, 2012

Filed:

Oct 31, 2011

Appl. No.:

13/286012

Inventors:

Paul Roger Stonelake - Santa Clara CA, US
Douglas Alan Prins - Laguna Hills CA, US
Anand Krisnamurthi Kulkarni - San Jose CA, US

International Classification:

G06F 12/00

US Classification:

711103, 711E12008

Abstract:

Methods and systems are disclosed for protecting metadata from NAND flash failures. With data striped across multiple flash memory chips, the flash memory multiple chips may store multiple copies of metadata (and potentially ECC). The metadata stored in the multiple copies on the flash memory chips may be different from one another. For example, on a particular chip, a first copy of metadata is stored and a second copy of metadata is stored, with the second copy being a redundant copy of the metadata stored on a different chip. In this way, if one of the chips fails, a copy of the failed chips metadata is stored on another of the chips, and may be accessed.

US Patent:

20120324276, Dec 20, 2012

Filed:

Oct 31, 2011

Appl. No.:

13/285873

Inventors:

Jack Edward Frayer - Boulder Creek CA, US
Aaron Keith Olbrich - Morgan Hill CA, US
Paul Roger Stonelake - Santa Clara CA, US
Anand Krishnamurthi Kulkarni - San Jose CA, US
Yale Yueh Ma - Palo Alto CA, US

International Classification:

G06F 11/16

US Classification:

714 611, 714E11055

Abstract:

A method and system intelligent bit recovery is provided. The intelligent bit recovery determines which bits are toggling, and examines a subset of the potential bit patterns to determine which in the subset of potential bit patterns is valid. The subset is a fraction of the potential bit patterns, and is based on an understanding of the flash memory and the problems that may cause the toggling bits. The intelligent bit recovery may analyze at least one aspect of the flash memory to identify which problem is potentially causing the toggling bits, and to select the subset of potential bit patterns as solutions for the determined problem. Or, the intelligent bit recovery selects potential bit patterns for multiple potential problems. In either way, the subset of potential bit patterns examined by the intelligent bit recovery is a small fraction of the entire set of potential bit patterns.

US Patent:

7188225, Mar 6, 2007

Filed:

Jul 28, 2004

Appl. No.:

10/900998

Inventors:

Christophe Therene - Livermore CA, US
Paul R. Stonelake - Santa Clara CA, US
Alex Ga Hing Tang - Fremont CA, US
Richard L. Harris - San Jose CA, US

Assignee:

Applied Micro Circuits Corporation - San Diego CA

International Classification:

G06F 12/00

US Classification:

711164, 711152, 711163, 711112, 711113, 711114

Abstract:

A disk array controller reliably detects disk drive power-on-reset events that may cause a disk drive that has uncommitted write data stored in its cache to lose such data. The methods for detecting the power-on-reset events include operating the disk drives in an ATA security mode in which a power-on-reset of a disk drive will cause the drive to enter a locked state in which data transfer commands are aborted; and tracking power cycle count attributes of the disk drives over time. When a disk drive power-on-reset event is detected, the disk array may be efficiently restored to an operational state by re-executing or “replaying” a set of write commands that are cached within the disk array controller. The invention is also applicable to single-disk-drive storage systems.

US Patent:

20220283949, Sep 8, 2022

Filed:

May 25, 2022

Appl. No.:

17/824685

Inventors:

- Boise ID, US
Paul Stonelake - San Jose CA, US
Samir Mittal - Palo Alto CA, US
Gurpreet Anand - Pleasanton CA, US

International Classification:

G06F 12/0868
G06F 13/28
G06F 3/06
G06F 13/16
G06F 13/42

Abstract:

A processing device in a host system monitors a data temperature of a plurality of memory pages stored in a host-addressable region of a cache memory component operatively coupled with the host system. The processing device determines that a first memory page of the plurality of memory pages satisfies a first threshold criterion pertaining to the data temperature of the first memory page and sends a first migration command indicating the first memory page to a direct memory access (DMA) engine executing on a memory-mapped storage component operatively coupled with the cache memory component and with the memory-mapped storage component via a peripheral component interconnect express (PCIe) bus. The first migration command causes the DMA engine to initiate a first DMA transfer of the first memory page from the cache memory component to a host-addressable region of the memory-mapped storage component.

US Patent:

20210311665, Oct 7, 2021

Filed:

Jun 22, 2021

Appl. No.:

17/304522

Inventors:

- Boise ID, US
Anirban Ray - Santa Clara CA, US
Gurpreet Anand - Pleasanton CA, US
Samir Rajadnya - San Jose CA, US
Paul Stonelake - Santa Clara CA, US
Samir Mittal - Palo Alto CA, US

International Classification:

G06F 3/06
G06F 13/42
G06F 13/16

Abstract:

A processing device, operatively coupled with one or more memory devices, is configured to provide a plurality of virtual memory controllers, partition one or more memory devices into a plurality of physical partitions, and associate each of the plurality of virtual memory controllers with one of the plurality of physical partitions. The processing device further provides a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers, and presents the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface.