Paul Francis Swartz

US Patent:

7305604, Dec 4, 2007

Filed:

Mar 4, 2005

Appl. No.:

11/072871

Inventors:

Himanshu J. Verma - Mountain View CA, US
Ajay Dalvi - San Francisco CA, US
Paul A. Swartz - Hillsborough CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G01R 31/28

US Classification:

714744

Abstract:

First and second clock signals are provided to first and second sequential circuits, where the first and second clock signals are inversely coupled to logic high and low levels for clocking of the first and second sequential circuits. A third sequential circuit is clocked responsive to a first output from the first sequential circuit and receives first signature data. A fourth sequential circuit is clocked responsive to a second output from the second sequential circuit and receives second signature data. A third output from the third sequential circuit is monitored responsive to the first signature data and the first output. A fourth output from the fourth sequential circuit is monitored responsive to the second signature data and the second output. Whether the first clock signal and the second clock signal are phase aligned may be determined responsive to the third output and the fourth output.

US Patent:

7308632, Dec 11, 2007

Filed:

Aug 11, 2005

Appl. No.:

11/201462

Inventors:

Himanshu J. Verma - Mountain View CA, US
Paul T. Nguyen - Fremont CA, US
Paul A. Swartz - Hillsborough CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G01R 31/28
H03K 3/017
H03K 7/08
H03H 11/26

US Classification:

714731, 327175, 327265

Abstract:

A method and apparatus for the utilization of on-chip, programmable resources to implement a signal distortion characterization circuit. Programmable logic resources, such as programmable delay lines and phase shifting circuits, are utilized to sample the logic value of a test signal after the test signal has traversed a path under test (PUT). A counter is used to determine the number of logic high valued samples and the number of logic low valued samples during a test period. A ratio is then taken to determine the resulting duty cycle for the test period.

US Patent:

7370245, May 6, 2008

Filed:

Feb 25, 2005

Appl. No.:

11/066685

Inventors:

Himanshu J. Verma - Mountain View CA, US
Ajay Dalvi - San Francisco CA, US
Paul A. Swartz - Hillsborough CA, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

G06K 5/04

US Classification:

714700

Abstract:

Cross-correlation of delay line characteristics is described. An integrated circuit for cross-correlation testing includes: a first ring oscillator and a second ring oscillator. The first ring oscillator includes a first test circuit, and the second ring oscillator includes a second test circuit. The first test circuit is coupled via first programmable interconnects to first ring oscillator circuitry, and the second test circuit is coupled via second programmable interconnects to second ring oscillator circuitry. The first test circuit includes a first programmable delay line, and the second test circuit includes a second programmable delay line. The first test circuit and the second test circuit are configured to provide separately controllable outputs for cross-correlation as between the first programmable delay line and the second programmable delay line.

US Patent:

7373560, May 13, 2008

Filed:

Dec 8, 2004

Appl. No.:

11/008474

Inventors:

Christopher H. Kingsley - San Jose CA, US
Kusuma Bathala - San Jose CA, US
Richard D. J. Duce - San Jose CA, US
Paul A. Swartz - Hillsborough CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G11B 5/00

US Classification:

714700, 714707

Abstract:

A system measures propagation delays in any number of test circuits, each having two asynchronous inputs and an output, without using their clock inputs to re-initialize the test circuits during measurement operations. The delay between one of the test circuit's asynchronous inputs and its output is measured by propagating a test signal from the one asynchronous input to the output, and the test circuit is re-initialized using the test circuit's other asynchronous input.