Pavanish B Nirula

US Patent:

7240315, Jul 3, 2007

Filed:

Aug 29, 2003

Appl. No.:

10/651789

Inventors:

Qiang Wang - Campbell CA, US
Sudip K. Nag - San Jose CA, US
Srinivasan Dasasathyan - Sunnyvale CA, US
James L. Saunders - Mountain View CA, US
Pavanish Nirula - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 9/45
G06F 17/50

US Classification:

716 10, 716 9

Abstract:

A method () of placing local clock nets in a circuit design can include identifying the local clock nets for the circuit design and selecting components corresponding to each local clock net (), and assigning initial locations to each component of the local clock nets (). The method further can include generating at least one cost function () to evaluate () different placements of components of the local clock nets. The components () of the local clock nets () can be annealed () using one or more of the cost functions to assign locations to each component of the local clock nets.