Pei Lun Lin

US Patent:

55965059, Jan 21, 1997

Filed:

Jul 23, 1993

Appl. No.:

8/096130

Inventors:

Russell L. Steinweg - Santa Clara CA
Michael A. Zampaglione - San Jose CA
Pei H. Lin - San Jose CA

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

G06F 1750

US Classification:

364490

Abstract:

A method for producing an electrical circuit by determining the input-to-output timing of compiled circuit blocks includes steps of determining a signal delay of a component due to physical characteristics of the component. The physical characteristics include at least a capacitance based upon relative placement of the component during compilation of a circuit block. The method further includes steps of determining an input-to-output speed for a circuit block by combining delays due to physical characteristics through alternate paths of the circuit block, and producing a compiled circuit block having a plurality of components by placing the components in the circuit block based on the steps of determining.

US Patent:

56257970, Apr 29, 1997

Filed:

Nov 3, 1993

Appl. No.:

8/148420

Inventors:

Thomas V. Ferry - San Jose CA
Russell L. Steinweg - Santa Clara CA
Michael A. Zampaglione - San Jose CA
Pei H. Lin - San Jose CA

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

G06F 1202

US Classification:

39549704

Abstract:

A block compiler system that allows a user to specify the total number of words and bits per word in a memory structure and to choose among alternative memory structures according to a user-selected criterion. In operation, the system varies the partitioning of memory address lines among column address lines and row address lines. Further, the system varies the internal memory structure according to a selected partitioning of memory address lines among column address lines and row address lines, and optimizes the memory structure based upon higher-level user-selected criteria.

US Patent:

54503310, Sep 12, 1995

Filed:

Jan 24, 1992

Appl. No.:

7/825490

Inventors:

Pei Lin - San Jose CA
Herve G. Duprez - Campbell CA

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

G06F 1560

US Classification:

364490

Abstract:

The present invention is directed to methods to assist designing integrated circuits by verifying that design constraints (e. g. , minimum path width) are satisfied between two arbitrary nodes of a circuit layout. In an exemplary embodiment, a method for designing an integrated circuit layout by verifying that predetermined design constraints are satisfied for an arbitrary path defined by at least two nodes, comprises the steps of labeling all polygons of the integrated circuit layout with a name which corresponds to a layer of the integrated circuit layout in which each polygon is located, creating a file of polygons which includes polygons located along the arbitrary path, and determining whether polygons located along the arbitrary path satisfy predetermined design constraints specified for that path.