Peter Bloch

US Patent:

6523006, Feb 18, 2003

Filed:

Jan 27, 1998

Appl. No.:

09/013848

Inventors:

David G. Ellis - Hillsboro OR
Louis J. Johnson - Aloha OR
Balaji Parthasarathy - Hillsboro OR
Peter B. Bloch - Portland OR
Steven R. Fordyce - Salem OR
Bill Munson - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G10K 1308

US Classification:

704270, 382110, 340435

Abstract:

Video data is received from multiple video receptors. This multidimensional video data is converted from the video receptors into a multidimensional audio representation of the multidimensional video data and are the multidimensional audio representation is output using multiple audio output devices. The conversion of the multidimensional video data includes generating a three-dimensional representation of the multidimensional video data, and generating an audio landscape representation with three-dimensional features based on the three-dimensional representation.

US Patent:

20010050710, Dec 13, 2001

Filed:

Jan 7, 1998

Appl. No.:

09/004051

Inventors:

DAVID G. ELLIS - HILLSBORO OR, US
LOUIS J. JOHNSON - ALOHA OR, US
BALAJI R. PARTHASARATHY - FT. COLLINS CO, US
PETER B. BLOCH - PORTLAND OR, US
STEVEN R. FORDYCE - SALEM OR, US
BILL A. MUNSON - PORTLAND OR, US

Assignee:

MARK J. FINK

International Classification:

H04N007/14

US Classification:

348/211000, 348/014080

Abstract:

An audio sensitive video conferencing camera is disclosed. The video conferencing camera includes a servo mechanism that operates to directionally position the video conferencing camera, and a processor that operates to control the servo mechanism to directionally position the video conferencing camera responsive to audio sensed.

US Patent:

62566873, Jul 3, 2001

Filed:

Aug 4, 1998

Appl. No.:

9/128956

Inventors:

David G. Ellis - Hillsboro OR
Gene A. Frederiksen - Hillsboro OR
Peter B. Bloch - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

710 71

Abstract:

The present invention is directed to a method and apparatus for managing data flow between a serial bus device which operates at a first data rate and a parallel port device which operates at a second data rate. A serial bus receiver receives data from the serial bus device at the first data rate. A buffer unit is coupled to the serial bus receiver and the parallel port device. The buffer unit stores the received data at the first data rate and transfers the stored data to the parallel port device at the second data rate.

US Patent:

59231939, Jul 13, 1999

Filed:

Dec 11, 1996

Appl. No.:

8/764608

Inventors:

Peter Bernhardt Bloch - Portland OR
Leonard William Cross - Portland OR
David Richard Jackson - Hillsboro OR
Ali Serhan Oztaskin - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 5135

US Classification:

327141

Abstract:

Briefly, in accordance with one embodiment, an integrated circuit includes: electronic circuitry for transferring digital data signals along a digital data signal path between different clock timing domains. The clock timing domains have a common higher frequency source clock. A first clock timing domain clock signal has a relatively fixed phase and a second clock timing domain clock signal has a relatively varying phase. The electronic circuitry includes delay elements in clock signal paths associated with the digital data signal path so that along the digital data signal path, clock signals in different clock timing domains are respectively staggered for a relatively short time compared with a given cycle of the source clock. The electronic circuitry further includes a digital data signal path including a data value retention element to delay the transfer of digital data signals between different clock timing domains at selected times.

US Patent:

60584408, May 2, 2000

Filed:

Sep 5, 1997

Appl. No.:

8/926314

Inventors:

Peter Bloch - Portland OR
Leonard W. Cross - Portland OR
Ali S. Oztaskin - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1342

US Classification:

710 60

Abstract:

A method and device is provided for controlling access to a resource by a bus master over a bus coupling the bus master to the resource. The resource includes an intelligent component that controls the operation of the resource. A series of packets is transmitted over the bus between the bus master and the resource, at a transmission speed controlled by the bus master. A request/response logic in the resource controllably throttles transmissions of the packets at the resource, at specified time intervals. Each of the time intervals is set at a time period to assure sufficient time for the intelligent component to complete processing tasks contained in the packets.