Sr. Desktop Analyst at Xilinx, Owner at Fast Pace Racing
Location:
San Francisco Bay Area
Industry:
Information Technology and Services
Work:
Xilinx since Sep 2007
Sr. Desktop Analyst
Fast Pace Racing - 2090 Duane Ave since Aug 2008
Owner
Universitiy of California Jan 2005 - Jun 2007
Technical Desktop Support
Education:
University of California, Davis 2003 - 2007
Bachelor of Science (BS), Minor Computer Sciences and Majoring in Natural Sciences and Geology
Interests:
Radio Controlled Technology, Robotics, Aerodynamics
Languages:
Vietnamese
Awards:
PGP Project Roll Out Excellence Award Xilinx Inc. Given to the PGP project team for superior communication and success it the deployment of PGP company wide. Honoring 5 Years of Employment Xilinx Given to Xilinx Emxployees that have worked for 5 years.
Phuc Thanh Tran - Fremont CA, US Bing Xiao - San Jose CA, US Tze Lei Poo - Sunnyvale CA, US Peter Nhat Dinh - San Jose CA, US
Assignee:
Marvell International Ltd.
International Classification:
G06F 7/04 G06F 12/14
US Classification:
726 17
Abstract:
Devices, systems, methods, and other embodiments associated with processing commands according to authorization are described. In one embodiment, a chip includes a secure module configured to store secure firmware, and to execute the secure firmware. The secure firmware prevents the secure module from at least partially processing a command that originated from an untrusted source. The chip also includes an unsecure module configured to store unsecure firmware, and to execute the unsecure firmware. The unsecure firmware permits the unsecure module to process a command having originated from an untrusted source. The chip is configured where the unsecure firmware is separately updateable from the secure firmware.
Security System With An Intelligent Dma Controller
George Apostol Jr - Santa Clara CA, US Peter Dinh - San Jose CA, US
International Classification:
H04K001/00
US Classification:
380255000
Abstract:
A security subsystem is provided with at least a first security engine, a first set of registers and a control portion to perform a first security operation for each of a first number of data blocks of each of a first number of data segments of a first data object. In one embodiment, the security subsystem is provided with two security engines and two sets of registers to respectively perform the first security operation and a second security operation for the first data object and a similarly constituted second data object. In one embodiment, the first and second security operations are DES and hashing operations. In one embodiment, the multi-method security subsystem is embodied in a multi-service system-on-chip.