Peter H Gum from 22 Miron Dr, Poughkeepsie, NY 12603, age 89, Phone: 8454620586

Resumes

Peter Gum

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Us Patents

System For Transferring Data Between I/O Devices And Main Or Expanded Storage Under Dynamic Control Of Independent Indirect Address Words (Idaws)
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US Patent:

54617219, Oct 24, 1995
Filed:

Apr 14, 1993
Appl. No.:

8/046679
Inventors:

Roger L. Cormier - Pleasant Valley NY
Robert J. Dugan - Hyde Park NY
Kenneth J. Fredericks - Poughkeepsie NY
Peter H. Gum - Poughkeepsie NY
Moon J. Kim - Wappingers Falls NY
Allen H. Preston - Poughkeepsie NY
Richard J. Schmalz - late of Wappingers Falls NY
Charles F. Webb - Poughkeepsie NY
Leslie W. Wyman - Poughkeepsie NY
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 1208
G06F 1210
US Classification:

395275
Abstract:

Enables an I/O channel program to use IDAWs (indirect data address words) to control data transfers from/to an I/O (input/output) device to/from either or both of ES (expanded storage) and/or system MS (main storage), in which data moved to/from ES does not move through MS. ES and MS are plural electronic storage media in a data processing system, and the I/O device is any I/O device selectable by the system. Intermixing of data transfers between ES and MS may be controlled by a single IDAW list accessed by a channel control word (CCW) in a channel program in a data transfer direction indicated in the CCW without any channel mode change.

Cpu Expansive Gradation Of I/O Interruption Subclass Recognition
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US Patent:

52222152, Jun 22, 1993
Filed:

Aug 29, 1991
Appl. No.:

7/752149
Inventors:

Norman C. Chou - Poughkeepsie NY
Peter H. Gum - Poughkeepsie NY
Roger E. Hough - Highland NY
Moon J. Kim - Fishkill NY
James C. Mazurowski - Poughkeepsie NY
Donald W. McCauley - Pleasant Valley NY
Casper A. Scalzi - Poughkeepsie NY
John F. Scanlon - Hyde Park NY
Leslie W. Wyman - Poughkeepsie NY
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 1300
US Classification:

395275
Abstract:

A CPU interface recognizing a large very number of I/O interruption queues in a logically partitioned data processing system. Different partitions may contain different guest operating systems. The CPU interface controls how plural CPUs respond to I/O interruptions put on numerous hardware-controlled queues. A host hypervisor program dispatches the guest operating systems. The guests use the I/O interruptions in controlling the dispatching of their programs on the CPUs in a system. The invention allows the number of guest partitions in the system to exceed the number of I/O interruption subclasses (ISCs) architected in the system, and enables the dispatching controls of each guest operating system to be sensitive to different priorities for plural programs operating under a respective guest. The invention provides CPU controls that support alerting the host to enabled I/O interruptions, and provides CPU controlled pass-through for enabling direct guest handling of the guests I/O interruptions.

Method And Means For Switching System Control Of Cpus
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US Patent:

44941897, Jan 15, 1985
Filed:

Apr 26, 1982
Appl. No.:

6/371754
Inventors:

George H. Bean - Hyde Park NY
Peter H. Gum - Poughkeepsie NY
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 910
US Classification:

364200
Abstract:

The embodiment obtains rapid switching between system control programs (SCPs) by switching an address in a prefix register in a CPU of a MP or UP data processing system from a guest SCP's PSA (program save area) to a host SCP's PSA by fetching the host prefix value from a predetermined control block in main storage. The prefix register loading changes the control of the CPU from a preferred guest SCP to a host SCP. This SCP switching is done by hardware and/or microcode means in the CPU. It further detects preset states in the CPU that enable a rapid determination of which SCP is to handle a sensed event, permitting the guest SCP to immediately handle events predetermined to belong to the guest. This manner of CPU control obtains for a preferred guest SCP (such as MVS/370) operating under a host SCP (such as VM/370) nearly the efficiency of standalone execution on the CPU by the preferred guest SCP.

Data Processing Control Of Second-Level Quest Virtual Machines Without Host Intervention
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US Patent:

53815351, Jan 10, 1995
Filed:

Nov 9, 1993
Appl. No.:

8/150332
Inventors:

Peter H. Gum - Poughkeepsie NY
Roger E. Hough - Highland NY
Robert E. Murray - Woodstock NY
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 1200
US Classification:

395375
Abstract:

A data processing system operated with multiple levels of virtual machine guests under a host control program. The second level of guests are invoked, operated, and terminated without host intervention, as has been required in prior systems, to significantly increase the operating efficiency of the system. Address translation is done by providing machine capability to translate second level guest addresses to real memory addresses taking advantage of the first level guest being located at a simple offset within real memory. Special facilities for second level guests periodically test for timing interruptions for second level guests and update the second level guest timing facilities.

Multi-Zone Relocation Facility Computer Memory System
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US Patent:

56528531, Jul 29, 1997
Filed:

May 31, 1995
Appl. No.:

8/455818
Inventors:

Karl Jean Duvalsaint - Hyde Park NY
Peter Hermon Gum - Poughkeepsie NY
Moon Ju Kim - Wappingers Falls NY
Barry Watson Krumm - Poughkeepsie NY
Donald William McCauley - Pleasant Valley NY
John Fenton Scanlon - Hyde Park NY
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 1210
US Classification:

395406
Abstract:

A memory reconfiguration system now allows a guest's absolute storage space to be mapped to multiple discontiguous host absolute storage space. A multi-zone relocation facility is provided for relocating multiple zones of the memory of the computer system. A control program being executed in its data processing system to reconfigure storages that are assigned to guests when sufficient real addressing capability is not available to provide a range of holes in the host absolute addressing space. Memory can be reconfigured by a control program that allows main storage, and expanded storage associated with a guest's real storage to be mapped to multiple discontiguous areas of host absolute spaces. When sufficient real addressing is not available in the host absolute addressing space it allows expansion of the host absolute storage space that maps a guest storage. The system can be used in scalar, parallel and massively parallel computer systems having plural logical processors (LPARs).

Logical Resource Partitioning Of A Data Processing System
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US Patent:

48435414, Jun 27, 1989
Filed:

Jul 29, 1987
Appl. No.:

7/079314
Inventors:

George H. Bean - Kingston NY
Terry L. Borden - Poughkeepsie NY
Mark S. Farrell - Pleasant Valley NY
Peter H. Gum - Poughkeepsie NY
Roger E. Hough - Highland NY
Francis E. Johnson - Poughkeepsie NY
Donald W. McCauley - Hopewell Junction NY
Mark E. Rakhmilevich - Kingston NY
John C. Rathjen - Rhinebeck NY
Casper A. Scalzi - Poughkeepsie NY
John F. Scanlon - Hyde Park NY
Leslie W. Wyman - Poughkeepsie NY
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 1516
US Classification:

364200
Abstract:

The embodiment discloses a method and means for partitioning the resources in a data processing system into a plurality of logical partitions. Host control code may be embodied in programming, microcode, or by special hardware to enable highly efficient operation of a plurality of preferred guest programming systems in the different partitions of the system. The main storage, expanded storage, the channel, and subchannel resources of a system are assigned to the different logical partitions in the system to enable a plurality of preferred guest programming systems to run simultaneously in the different partitions. This invention automatically relocates the absolute addresses of the I/O channel and subchannel resources in the system to their assigned partitions. Also the absolute and virtual addresses of the different guest programming systems are relocated into, as well as page addresses for any expanded storage, their assigned partitions. The guest programming systems generally will be different operating systems.

Selective Guest System Purge Control
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US Patent:

47791888, Oct 18, 1988
Filed:

Oct 19, 1987
Appl. No.:

7/110620
Inventors:

Peter H. Gum - Poughkeepsie NY
Roger E. Hough - Highland NY
Peter H. Tallman - Poughkeepsie NY
Thomas O. Curlee - Poughkeepsie NY
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 944
G06F 932
US Classification:

364200
Abstract:

The embodiments enable address translations for a virtual machine in the TLB (translation lookaside buffer) of a CPU to be retained from exiting a SIE (start interpretive execution) instruction to the next SIE entry to interpretive execution for the same guest (virtual machine CPU). Conditions are defined which determine when guest TLB entries must be invalidated. These conditions require invalidation of guest TLB entries only within and on entry to interpretive execution. A single invalidation of guest TLB entries on entry to interpretive execution is required for any number of conditions recognized while a CPU is not in interpretive execution state. For a guest in a virtual multi-processor (MP) machine, an interlock is provided to allow the use of guest virtual addresses by host instruction simulation and the need for guest TLB invalidation is broadcast to all other real CPUs in a real MP system so that all guest TLBs on all real CPUs can be invalidated to maintain integrity. No broadcast or interlock is needed for a guest in a virtual uni-processor (UP) machine.

Scheduling Normally Interchangeable Facilities In Multiprocessor Computer Systems
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US Patent:

54045630, Apr 4, 1995
Filed:

Jan 14, 1994
Appl. No.:

8/181379
Inventors:

Lucina L. Green - Verbank NY
Peter H. Gum - Poughkeepsie NY
Roger E. Hough - Stormville NY
Sandra L. Rankin - Stormville NY
Stephen J. Schmandt - Tokyo, JP
Ronald M. Smith - Wappingers Falls NY
Vincent A. Spano - Poughkeepsie NY
Phil C. Yeh - Poughkeepsie NY
Devon S. Yu - Poughkeepsie NY
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 900
G06F 1120
US Classification:

395800
Abstract:

A system and method for dispatching logical central processing units (CPUs) among physical CPUs in a multiprocessor computer system having multiple logical partitions, wherein the cryptographic facilities may not be interchangeable. According to the present invention, the logical CPUs are dispatched among the physical CPUs according to either an affinity, floating, or disabled scheduling method. The affinity scheduling method is used when the crypto facilities are not interchangeable or when non-interchangeable crypto functions are performed. The floating scheduling method is used when the cryptographic facilities are interchangeable and interchangeable crypto functions are performed. The disabled scheduling method is used when the logical CPU is not authorized to issue cryptographic instructions.