Peter K Hazen

US Patent:

6510083, Jan 21, 2003

Filed:

May 2, 1997

Appl. No.:

08/850644

Inventors:

Deborah L. See - Placerville CA
Peter K. Hazen - Auburn CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 700

US Classification:

36518524, 36518503, 36518509, 36518522, 365201

Abstract:

A processor-implemented method is described for updating a datum stored in a nonvolatile memory, bits of which cannot be overwritten from a first logical state to a second logical state without a prior erasure. A first storage location in the memory that stores a first version of the datum is accessed. A status field of the first storage location is checked to determine whether the first version of the datum has been superseded. If the status field of the first storage location indicates that the first version of the datum has not been superseded, then a most recent version of the datum is stored in a second storage location of the memory. An address of the second storage location is then written into a next location address field of the first storage location and the status field of the first storage location is written to indicate that the first version of the datum has been superseded such that the datum is updated without the prior erasure of the memory. If the status field of the first storage location indicates that the first version of the datum has been superseded, then the next location address field of the first storage location is accessed to obtain the address of a next storage location that stores a second version of the datum that supersedes the first version of the datum. The next storage location is then caused to be the first storage location and the method repeats itself to access the first storage location.

US Patent:

6633950, Oct 14, 2003

Filed:

Sep 1, 2000

Appl. No.:

09/653768

Inventors:

Charles W. Brown - Folsom CA
Peter K. Hazen - Auburn CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711103

Abstract:

A method and apparatus for preempting an operation in a nonvolatile writeable memory is performed using a pin. Preempting an operation is accomplished by either suspending the operation or by aborting the operation. Once an operation is suspended in the nonvolatile writeable memory, other operations can then be performed. Subsequently the suspended operation may be resumed.

US Patent:

55946860, Jan 14, 1997

Filed:

Dec 29, 1995

Appl. No.:

8/578175

Inventors:

Peter K. Hazen - Auburn CA
Michael J. Castillo - Provo UT

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 1134

US Classification:

36518504

Abstract:

A method and apparatus for protecting data stored in a nonvolatile memory. First, a locking signal is initiated to indicate to the memory that write and erase operations are to be prevented. Next, in response to this locking signal, the supply voltage that supports write and erase operations in the memory is lowered below a threshold value. In doing so, protection circuitry that is contained within the memory prevents write and erase operations in the memory.

US Patent:

61548197, Nov 28, 2000

Filed:

May 11, 1998

Appl. No.:

9/076298

Inventors:

Robert E. Larsen - Shingle Springs CA
Peter Hazen - Auburn CA
Sanjay S. Talreja - Folsom CA
Sandeep Guliani - Folsom CA
Robert N. Hasbun - Placerville CA
Collin Ong - Sacramento CA
Terry D. West - Chandler AZ
Charles Brown - Folsom CA
Terry L. Kendall - Diamond Springs CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1214

US Classification:

711163

Abstract:

An apparatus for protecting memory blocks in a block-based flash Erasable Programmable Read Only Memory (EPROM) device is disclosed. A non-volatile memory array includes a number of blocks that are capable of being placed in a locked state or an unlocked state. A volatile lock register and transmits a write protect signal and a volatile lock-down register are coupled to a lockable block in the volatile memory array. A hardware override line is coupled to both the lock register and the lock-down register. The hardware override line temporarily overrides operation of the lock-down register when it transmits a signal at a first logic state. The lock down register may be used to prevent programming of an associated lock register. The lock registers and lock down registers may be embodied in static access memory (SRAM) circuits. A command buffer may be operable to transmit a two cycle command including a first command specifying whether a lock configuration is to be changed and a second command specifying whether a block is to be placed in a lock state, an unlock state, or locked down state.

US Patent:

52742784, Dec 28, 1993

Filed:

Dec 31, 1991

Appl. No.:

7/816155

Inventors:

Mark E. Bauer - Cameron Park CA
Peter Hazen - Sacramento CA
Sherif Sweha - El Dorado Hills CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 1920
H03K 19082

US Classification:

307449

Abstract:

In a memory array in which logic signals of a first and a second voltage levels are used for selecting memory positions in the array for read operations and at least one signal of a voltage level higher than the first and second voltage levels may appear, and including a plurality of wordlines each joined to a common node by individual row decoders, a predecoder circuit for selecting a plurality of wordlines from which a row decoder may select an individual wordline including a full CMOS NAND gate arranged to provide output voltage levels of the first and a second voltage levels, a plurality of weak P channel devices each connected to one of the wordlines, means for operating the weak P channel devices to provide voltage levels of the higher level and below at the wordlines, means for limiting value of voltage transferred to the common point to be less than the higher voltage level, and means for limiting the level of the voltage transferred to the common node from the NAND gate to be less than a predetermined level.

US Patent:

56687605, Sep 16, 1997

Filed:

Apr 23, 1996

Appl. No.:

8/636529

Inventors:

Peter K. Hazen - Auburn CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 700
G11C 800

US Classification:

36518901

Abstract:

A nonvolatile memory includes a memory array and a control circuit having a command latch and a command decoder. The control circuit receives an output enable signal and a write enable signal to control memory operations of the memory array in accordance with a command latched into the command latch via the command decoder. A write protection circuit is also provided that disables the command latch and the command decoder when the output and write enable signals are both active. The protection circuit includes a pulse generator that generates a reset signal to reset the command latch to the read array state and a control logic that causes the pulse generator to assert the reset signal when an output enable signal and a write enable signal of the memory are both active until after the write enable signal has been forced internally inactive and the command latch closed.

US Patent:

59408618, Aug 17, 1999

Filed:

Sep 20, 1996

Appl. No.:

8/717268

Inventors:

Charles W. Brown - Folsom CA
Peter K. Hazen - Auburn CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1202

US Classification:

711154

Abstract:

A method and apparatus suspend operations in a flash memory in order to read code from the flash memory. A system comprises a processor and a nonvolatile writeable memory coupled together. A non-read operation is preempted in the nonvolatile writeable memory responsive to an input at a pin of the nonvolatile writeable memory. The preemption occurs by either suspending the non-read operation or aborting the non-read operation. Code is read from the nonvolatile writeable memory and provided to the processor. Subsequently, the non-read operation is resumed at where it was suspended, or is started anew.

US Patent:

61821896, Jan 30, 2001

Filed:

Jan 5, 1998

Appl. No.:

9/002691

Inventors:

Ranjeet Alexis - Folsom CA
Peter K. Hazen - Auburn CA
Charles W. Brown - Folsom CA
Robert E. Larsen - Shingle Springs CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

711103

Abstract:

An interface for a read-while-write memory. A memory device includes a single-chip memory array and an interface that is responsive to one or more commands to configure the memory array in a read-while-write configuration.