Peter J Johnston

US Patent:

7428075, Sep 23, 2008

Filed:

Jun 30, 2006

Appl. No.:

11/480221

Inventors:

Peter Johnston - San Mateo CA, US

Assignee:

Konica Minolta Systems Laboratory, Inc. - Huntington Beach CA

International Classification:

G06F 15/00
H04N 1/40

US Classification:

358 19, 358 301

Abstract:

The methods and systems presented herein use well-known logic devices in combination with one or more pulse-width-modulation (PWM) devices in order to create left- and right-justified width-modulated pulses. In some embodiments, justification ability is added without the need to alter an existing PWM device. In some embodiments, the generation of justified pulses is accomplished by a logic circuit in combination with an inherently left- or right-justified PWM device. Some embodiments of the present invention may include, for example, any combination of logical selectors, inverters, and flip-flops. In some embodiments, a justification circuit may receive as input any combination of one or more bits of pixel data, one or more bits of justification selection data, and one or more clock signal. In some embodiments, a justification circuit may output one more signals representing left or right-justified pulses.

US Patent:

7619644, Nov 17, 2009

Filed:

Jun 30, 2006

Appl. No.:

11/479562

Inventors:

Peter Johnston - San Mateo CA, US

Assignee:

Konica Minolta Systems Laboratory, Inc. - Foster City CA

International Classification:

B41J 2/435
B41J 2/47

US Classification:

347237, 347247

Abstract:

Apparatus, systems, and methods presented herein allow for the alignment of images. In some embodiments, a plurality of PWM modules each receive input data and corresponding input phase-shifted clock signals. In some embodiments, each PWM module generates an output phase-shifted PWM signal based on the input data and its corresponding input phase-shifted clock signal. In some embodiments, a selector selects one of the output phase-shifted PWM signal based on timing relationships between an event signal and the phase-shifted clock signals.

US Patent:

7822115, Oct 26, 2010

Filed:

Jun 30, 2006

Appl. No.:

11/479294

Inventors:

Peter Johnston - San Mateo CA, US

Assignee:

Konica Minolta Systems Laboratory, Inc. - Foster City CA

International Classification:

H03K 7/08
H03K 3/017

US Classification:

375238, 327172

Abstract:

Systems in accordance with the presently claimed invention use input data to create an output pulse that is a fraction of the width of an input pulse. In some embodiments, the invention accepts input data and an input signal that has pulses of a specific frequency. In some embodiments, the invention uses a phase lock loop to create multiple signals of a higher frequency than the frequency of the input signal. Each of these multiple signals is offset by a certain phase from the other signals. In some embodiments, the invention synchronizes the input data to each of these multiple signals. The invention uses the phase difference between the multiple signals to create an output pulse as a function of the input data that is a fraction of the width of the input pulse.

US Patent:

7907303, Mar 15, 2011

Filed:

Jun 30, 2006

Appl. No.:

11/479896

Inventors:

Peter Johnston - San Mateo CA, US

Assignee:

Konica Minolta Systems Laboratory, Inc. - Foster City CA

International Classification:

G06K 15/00
G06F 3/12

US Classification:

358 116, 358 11

Abstract:

An apparatus and method for processing pixel data is presented that includes a plurality of image forming modules coupled to a data control module. The data control module includes a plurality of memory units. Each memory unit can store a portion of an image. The data control module receives a first signal and a second signal and selects at least one of the plurality of image forming modules to send the image portions stored in the plurality of memory units based on a timing relationship between a first image alignment event on the first signal and a second image alignment event on the second signal.

US Patent:

7957025, Jun 7, 2011

Filed:

Jun 30, 2006

Appl. No.:

11/479596

Inventors:

Peter Johnston - San Mateo CA, US

Assignee:

Konica Minolta Systems Laboratory, Inc. - Foster City CA

International Classification:

H04N 1/00
G06K 15/22
G06K 15/00

US Classification:

358 16, 358 14, 358 15

Abstract:

An apparatus and method for processing pixel data is presented that includes an image forming apparatus that includes an image forming module coupled to a data control module that comprises a plurality of memory units, wherein each of the memory units stores a corresponding portion of pixel data of an image. The data control module writes out portions of pixel data stored in corresponding memory units to the image forming module and dynamically associates each memory unit with a further portion of pixel data after its corresponding portion of pixel data has been written out.

US Patent:

8068667, Nov 29, 2011

Filed:

Oct 30, 2008

Appl. No.:

12/261745

Inventors:

Peter Johnston - San Francisco CA, US

Assignee:

Konica Minolta Systems Laboratory, Inc. - Huntington Beach CA

International Classification:

G06K 9/00

US Classification:

382166

Abstract:

Systems and methods are provided for reducing data size of at least one bitmap image comprising at least one block, wherein the block comprises a plurality of image components, each image component being associated with a distinct color plane. The method may include compressing the plurality of image components of the at least one block. The method may further include ranking the plurality of image components using a dominance rank, wherein the dominance rank for an image component is based on a compression ratio for the image component. The method may also include reducing the resolution of at least one image component associated with the block, based on the dominance rank of the color plane associated with the image component.

US Patent:

8098942, Jan 17, 2012

Filed:

Jun 30, 2008

Appl. No.:

12/165596

Inventors:

Peter Johnston - San Francisco CA, US

Assignee:

Konica Minolta Systems Laboratory, Inc. - Tokyo

International Classification:

G36K 9/36
G36K 9/46
G36K 9/00
G36K 15/02

US Classification:

382232, 382235, 382116, 382239, 358 12

Abstract:

Systems and methods are provided for reducing data size of at least one bitmap image, wherein the bitmap image comprises a plurality of color blocks, wherein each color block is associated with a distinct color plane. In some embodiments, the bitmap image may be compressed. At least one compressed color block that is contained in a transfer frame may be determined, based on information pertaining to a physical offset between successive color planes when they are rendered on a print medium. Further, at least one compressed color block in the transfer frame may be tagged, if the size of the transfer frame exceeds a threshold, and the resolution of the at least one compressed color block that is tagged may be reduced.

US Patent:

8121435, Feb 21, 2012

Filed:

Mar 31, 2008

Appl. No.:

12/078415

Inventors:

Peter Johnston - San Francisco CA, US

Assignee:

Konica Minolta Laboratory U.S.A., Inc. - San Mateo CA

International Classification:

G06K 9/32

US Classification:

382299, 382235, 382243, 382275

Abstract:

Systems and methods are provided for switching a resolution of an image, wherein the image includes at least one block. In some embodiments, the image is compressed. At least one compressed block in the compressed image is tagged, if the data size of the compressed block exceeds a threshold. A non-transition region is grown based on the at least one compressed block that is tagged until a safe-transition block is reached, wherein the non-transition region includes the at least one compressed block in the compressed image. The resolution of each compressed block in the non-transition region is reduced.