Peter P Lai

US Patent:

6396149, May 28, 2002

Filed:

Jun 13, 2000

Appl. No.:

09/593284

Inventors:

Xuejun Yuan - San Jose CA
Xiaowei Jin - Mountain View CA
Rambabu Pyapali - Santa Clara CA
Raymond A. Heald - Los Altos CA
James M. Kaku - Palo Alto CA
Helen Dunn - San Jose CA
Thelma C. Taylor - San Jose CA
Peter F. Lai - Mountain View CA
Aharon Ostrer - Sunnyvale CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

H01L 2710

US Classification:

257758, 257202

Abstract:

In one aspect of the present invention, a method provides a connecting path diversion through an upper layer of an integrated circuit by alteration of a connecting path through a lower layer of the integrated circuit. This method enables a circuit path in an integrated circuit to be modified in an accessible layer for testing before the modified circuit path is incorporated in a redesigned integrated circuit design. In another aspect of the present invention, a modified multi-layer integrated circuit chip includes a connecting path formed in a lower layer and a substitute connecting path that is etched in the lower layer. Subsequently, the connecting path formed in the lower layer may be severed.

US Patent:

6596563, Jul 22, 2003

Filed:

Mar 4, 2002

Appl. No.:

10/091620

Inventors:

Xuejun Yuan - San Jose CA
Xiaowei Jin - Mountain View CA
Rambabu Pyapali - Santa Clara CA
Raymond A. Heald - Los Altos CA
James M. Kaku - Palo Alto CA
Helen Dunn - San Jose CA
Thelma C. Taylor - San Jose CA
Peter F. Lai - Mountain View CA
Aharon Ostrer - Sunnyvale CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H01L 2144

US Classification:

438118, 438652

Abstract:

In one aspect of the present invention, a method provides a connecting path diversion through an upper layer of an integrated circuit by alteration of a connecting path through a lower layer of the integrated circuit. This method enables a circuit path in an integrated circuit to be modified in an accessible layer for testing before the modified circuit path is incorporated in a redesigned integrated circuit design. In another aspect of the present invention, a modified multi-layer integrated circuit chip includes a connecting path formed in a lower layer and a substitute connecting path that is etched in the lower layer. Subsequently, the connecting path formed in the lower layer may be severed.

US Patent:

6654942, Nov 25, 2003

Filed:

Aug 22, 2001

Appl. No.:

09/938120

Inventors:

Sachin Chopra - Santa Clara CA
Peter Fu - Sunnyvale CA
Peter Lai - San Jose CA
Srirarm Satakopan - Sunnyvale CA
Hsiu-Nien Chen - San Jose CA
Von-Kyoung Kim - Santa Clara CA
Yongjun Zhang - Sunnyvale CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 1750

US Classification:

716 12, 716 14, 716 13

Abstract:

Method and system for providing a netlist driven integrated router in a non-netlist driven environment for microprocessor designs includes retrieving top level netlist for the existing microprocessor design from the top level database and the design parameters for the new microprocessor design, and translating these netlist and design parameters at the front end so that the resulting data can be provided to an integrated router which is configured to generate re-routes for the new microprocessor design based on the top level netlist and the design parameters, where the generated re-routes are provided to a back end for translating the re-routes to new top level netlist and merging the new top level netlist with the existing top level netlist database.

US Patent:

6775813, Aug 10, 2004

Filed:

Sep 10, 2002

Appl. No.:

10/238357

Inventors:

Sachin Chopra - Cupertino CA
Yu-Yen Mo - San Jose CA
Shyam Sundar - Sunnyvale CA
Peter F. Lai - San Jose CA
Venkat Podduturi - San Jose CA
Vishal Chopra - Cupertino CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 945

US Classification:

716 10, 716 8, 716 9

Abstract:

The present invention describes a method and apparatus for placing flops in a complex circuit design. Initially, the method calculates a physical range for every net that requires a flop, within which the flop can be placed satisfying the timing requirement. After the physical range is defined, the method groups these flops and determines a block where these grouped flops can be placed. Grouping these flops into one block (flop station) can preserve a compact layout for the design. The flops are then connected to appropriate nets.

US Patent:

6779131, Aug 17, 2004

Filed:

May 1, 2001

Appl. No.:

09/846943

Inventors:

Rambabu Pyapali - Santa Clara CA
Xuejun Yuan - Sunnyvale CA
Xiaowei Jin - Mountain View CA
Peter Lai - San Jose CA
Samer H. Haddad - Fremont CA
Jeffrey Wong - Fremont CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 1100

US Classification:

714 8

Abstract:

The present invention relates to a method and apparatus for a reconfigurable multi-chip module. The reconfigurable multi-chip module includes a processor; a memory module connected to the processor; and a memory control component for controlling whether the processor uses the memory module. The method of producing multi-chip modules includes assembling a processor and a memory module on the multi-chip module; testing the memory module; and selectively configuring the processor to use the memory module based on the testing of the memory module.

US Patent:

6954914, Oct 11, 2005

Filed:

Mar 24, 2003

Appl. No.:

10/395436

Inventors:

Shyam Sundar - Sunnyvale CA, US
Aveek Sarkar - Mountain View CA, US
Peter F. Lai - San Jose CA, US
Rambabu Pyapali - Cupertino CA, US
Teong Ming Cheah - Sunnyvale CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F017/50

US Classification:

716 5, 716 6, 716 2

Abstract:

The present application describes various embodiments of a method and an apparatus for determining electromigration risks for signal nets in integrated circuits. A model for each one of the global nets connecting various circuit blocks in an integrated circuit is created using circuit blocks' timing model and detailed standard parasitic format representation (DSPF) of each global net. The final layout of the integrated circuit is not necessary to determine the electromigration risks. The models can be generated during the early stages of the design cycle once the DSPF of the global nets is available.

US Patent:

7007256, Feb 28, 2006

Filed:

Mar 6, 2003

Appl. No.:

10/383092

Inventors:

Aveek Sarkar - Mountain View CA, US
Shyam Sundar - Sunnyvale CA, US
Peter F. Lai - San Jose CA, US
Rambabu Pyapali - Cupertino CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 9/45
G06F 9/455
G06F 17/50

US Classification:

716 6, 716 4, 716 11, 703 14, 703 19

Abstract:

The present invention describes a method and an apparatus for determining switching power consumption of global devices (e. g. , repeaters, flops or the like) in an integrated circuit design during high-level design phase after the global routing for the integrated circuit is available. The clock cycle is divided into various timing intervals and the timing reports are generated for each cycle to determine a time-domain staggered distribution of each device's switching activity within a given timing interval. Each device's switching activity is analyzed within the given timing interval (or segment thereof). The power consumption is determined for each device that switches in the given timing interval.

US Patent:

7032200, Apr 18, 2006

Filed:

Sep 9, 2003

Appl. No.:

10/657964

Inventors:

Sriram Satakopan - Sunnyvale CA, US
Arvindvel Shanmugavel - Mountain View CA, US
Shunjiang Xu - Sunnyvale CA, US
Von-Kyoung Kim - Santa Clara CA, US
Peter Lai - San Jose CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 17/50

US Classification:

716 6, 716 4, 716 5

Abstract:

A technique improves the performance of an integrated circuit design by selectively replacing low Vtransistors with standard Vtransistors. The selection of gates for replacement may be based on a multi-path timing analysis. If a low Vvariant of a gate instance increases a path cycle time as compared to a standard Vcounterpart, the maximum of the path cycle times for all paths that include the low Vvariant and the maximum of the path cycle time for these paths with a standard Vvariant are calculated. If the maximum path cycle time for the path including the low Vvariant is greater than the maximum path cycle time for the path including the standard Vvariant, then that low Vvariant is substituted with a standard Vvariant. Thus, integrated circuit designs prepared in accordance with the invention may exhibit improved cycle times.