Peter S Lenk

US Patent:

6587930, Jul 1, 2003

Filed:

Sep 23, 1999

Appl. No.:

09/404400

Inventors:

Sanjay Raghunath Deshpande - Austin TX
Peter Steven Lenk - Austin TX
Michael John Mayfield - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711144, 711145, 711122

Abstract:

A distributed system structure for a large-way, multi-bus, multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. The system allows for the implementation of a bus protocol that reports the state of a cache line to a master device along with the first beat of data delivery for a cacheable coherent Read. Since the achievement of coherency is distributed in time and space, the issue of data integrity is addressed through a variety of actions. In one implementation, the node controller helps to maintain cache coherency for commands by blocking a master device from receiving certain transactions so as to prevent Read-Read deadlocks.

US Patent:

7904612, Mar 8, 2011

Filed:

Jul 8, 2004

Appl. No.:

10/887438

Inventors:

Peter Steven Lenk - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/14
G06F 9/50

US Classification:

710 17, 710 5, 710 6, 710 15, 710 19, 718102, 718104

Abstract:

Improved administering of shared resources in a computer system. In a preferred embodiment, transaction throughput is improved and potential starvation eliminated by a ticket mechanism. The ticket mechanism provides a wait counter and a service counter. When a requested transaction fails, a wait counter is incremented and a wait value is sent to the requesting transaction source. As transactions are completed at the resource, the service counter is incremented and its value broadcast to transaction sources sharing that resource. When a source holds a wait count value that equals the service count value, the source can retry the transaction successfully.

US Patent:

20030120874, Jun 26, 2003

Filed:

Jan 17, 2003

Appl. No.:

10/347536

Inventors:

Sanjay Deshpande - Austin TX, US
Peter Lenk - Austin TX, US
Michael Mayfield - Austin TX, US

International Classification:

G06F012/08

US Classification:

711/141000, 711/145000, 711/146000, 711/122000

Abstract:

A distributed system structure for a large-way, multi-bus, multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. The system allows for the implementation of a bus protocol that reports the state of a cache line to a master device along with the first beat of data delivery for a cacheable coherent Read. Since the achievement of coherency is distributed in time and space, the issue of data integrity is addressed through a variety of actions. In one implementation, the node controller helps to maintain cache coherency for commands by blocking a master device from receiving certain transactions so as to prevent Read-Read deadlocks. In another implementation, the master devices use a bus protocol that prevents Read-Read deadlocks in a distributed, multi-bus, multiprocessor system.

US Patent:

60981563, Aug 1, 2000

Filed:

Jul 22, 1997

Appl. No.:

8/898323

Inventors:

Peter Steven Lenk - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1208

US Classification:

711146

Abstract:

A method and system according to the present invention of accessing data in a multiprocessor system including a plurality of processors and a memory, wherein the memory includes a plurality of memory locations, and wherein at least a first processor and a second processor each include a reservation indicator and a cache, each cache having a plurality of cache memory locations corresponding to the memory locations. The method and system comprises providing a Load And Reserve request from the first processor for at least one of the plurality of memory locations and determining whether the second processor includes at least one of the plurality of cache memory locations corresponding with the at least one of the memory locations; determining whether the second processor's reservation indicator is set, this determination being in response the second processor including the at least one of the cache memory locations corresponding with the at least one of the memory locations. The method and system also provides a state indicating that the at least one of the cache memory locations of the second processor corresponding to the at least one of the memory locations is invalid, responsive to the reservation indicator not being set.

US Patent:

61784931, Jan 23, 2001

Filed:

Feb 19, 1998

Appl. No.:

9/026088

Inventors:

Peter Steven Lenk - Austin TX
Michael J. Mayfield - Austin TX
Robert James Reese - Austin TX
Michael Thomas Vaden - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1500

US Classification:

712 28

Abstract:

In a multiprocessor system, when a store request has stalled, a signal is generated and sent to all processors indicating such a stalled store situation. In response, all processors will postpone the sending of load, or read, requests to memory until the stalled store request has completed.

US Patent:

62759183, Aug 14, 2001

Filed:

Mar 16, 1999

Appl. No.:

9/268307

Inventors:

William Elton Burky - Austin TX
Peter Steven Lenk - Austin TX
Dung Quoc Nguyen - Austin TX
David Andrew Schroter - Round Rock TX
Shih-Hsiung Stephen Tung - Austin TX
Michael Thomas Vaden - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 934

US Classification:

711213

Abstract:

A method and system for improving pre-fetch accuracy in a data processing system utilizing a pre-fetch history table is disclosed. The method compares a portion of an instruction address to an address located as an entry in a pre-fetch history table based on the status of a validity bit contained in the entry. If the validity bit is set and the addresses match, an indicator field within the entry is checked to see if it is equal to or greater than a threshold level. When the indicator field is greater than the threshold level, a target operand address is pre-fetched based on stride and direction.