Peter G Nicholas

US Patent:

8362803, Jan 29, 2013

Filed:

Feb 18, 2011

Appl. No.:

13/031176

Inventors:

Peter J. Nicholas - Philadelphia PA, US
John Christopher Kriz - Palmerton PA, US
Dipankar Bhattacharya - Macungie PA, US
James John Bradley - Broomfield CO, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H03K 19/0175

US Classification:

326 81, 326 68, 326 80

Abstract:

A voltage translator circuit includes an input stage adapted for receiving an input signal referenced to a first voltage supply, a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal, and a voltage clamp coupled between the input stage and the first latch circuit. The voltage clamp is operative to set a maximum voltage across the input stage to a prescribed level. The voltage translator circuit generates a first output signal at a first output formed at a junction between the first latch circuit and the voltage clamp. A second latch circuit is connected to the first output in a feedback configuration. The second latch circuit is operative to retain a logical state of the first output signal as a function of at least a first control signal supplied to the second latch circuit regardless of a state of the first voltage supply.