Phi L Nguyen

US Patent:

6472315, Oct 29, 2002

Filed:

Mar 14, 2001

Appl. No.:

09/808758

Inventors:

Phi L. Nguyen - Hillsboro OR
Lawrence D. Wong - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 214763

US Classification:

438637, 438638, 438672, 438725

Abstract:

A method for fabricating an interconnect system is provided. A low dielectric constant layer (LDCL) is formed onto a substrate. A hard mask is formed onto the LDCL. A patterning material is formed onto the hard mask. The patterning material is via patterned. A via pattern of the patterning material is transferred to the hard mask. The patterning material is stripped at a substantially low temperature. Vias are formed through the LDC using a via pattern formed in the hard mask.

US Patent:

6958547, Oct 25, 2005

Filed:

May 28, 2003

Appl. No.:

10/446749

Inventors:

Valery M. Dubin - Portland OR, US
Chin-Chang Cheng - Hillsboro OR, US
Makarem Hussein - Beaverton OR, US
Phi L. Nguyen - Hillsboro OR, US
Ruth A. Brain - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L023/48

US Classification:

257774, 257758, 257759, 438612, 438637, 438672

Abstract:

Multiple level interconnect structures and methods for fabricating the interconnect structures are disclosed. The interconnect structures may contain an interconnect line, an electrolessly deposited metal layer formed over the interconnect line, a via formed over the metal layer, and a second interconnect line formed over the via. Often the metal layer contains a cobalt or nickel alloy and provides an etch stop layer for formation of an opening corresponding to the via. The metal layer may provide protection to the underlying interconnect line and may replace a traditional protective dielectric layer. The metal layer is conductive, rather than dielectric, and provides a shunt for passage of electrical current between the via and the interconnect line. Similar metal layers may also be used within the interconnect structures as via liner layers and via plugs.

US Patent:

7008872, Mar 7, 2006

Filed:

May 3, 2002

Appl. No.:

10/139052

Inventors:

Valery M. Dubin - Portland OR, US
Chin-Chang Cheng - Hillsboro OR, US
Makarem Hussein - Beaverton OR, US
Phi L. Nguyen - Hillsboro OR, US
Ruth A. Brain - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/441

US Classification:

438678, 438627

Abstract:

Multiple level interconnect structures and methods for fabricating the interconnect structures are disclosed. The interconnect structures may contain an interconnect line, an electrolessly deposited metal layer formed over the interconnect line, a via formed over the metal layer, and a second interconnect line formed over the via. Often the metal layer contains a cobalt or nickel alloy and provides an etch stop layer for formation of an opening corresponding to the via. The metal layer may provide protection to the underlying interconnect line and may replace a traditional protective dielectric layer. The metal layer is conductive, rather than dielectric, and provides a shunt for passage of electrical current between the via and the interconnect line. Similar metal layers may also be used within the interconnect structures as via liner layers and via plugs.

US Patent:

58438467, Dec 1, 1998

Filed:

Dec 31, 1996

Appl. No.:

8/775573

Inventors:

Phi L. Nguyen - Hillsboro OR
Ralph A. Schweinfurth - Beverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21302

US Classification:

438713

Abstract:

The present invention describes a method for rounding the top corners of a sub-micron trench in a semiconductor device directly after trench formation. In one embodiment of the present invention the etch process uses an etchant made up of a carbon-fluorine gas, an argon gas, and a nitrogen gas. The combination of gases enables the rounding of the top corners of the trench directly after the trench is formed. The combination of the carbon-fluorine and nitrogen gases etch back the silicon nitride and stress relief oxide layers in order to expose the top corners of the trench. As the top corners of the substrate are exposed the nitrogen and argon gases sputter the top corners rounding them as the etch process completes the trench.

US Patent:

59337591, Aug 3, 1999

Filed:

Dec 31, 1996

Appl. No.:

8/778020

Inventors:

Phi L. Nguyen - Hillsboro OR
Ralph A. Schweinfurth - Beverton OR
Swaminathan Sivakumar - Hillsboro OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

C03C 1500
C03C 2506

US Classification:

438700

Abstract:

The present invention describes a method for forming submicron critical dimension shallow trenches with improved etch selectivity and etch bias control. In one embodiment of the present invention, three separate etch steps are performed. A polish stop layer (or an etch hard mask layer) and an oxide layer are etched during the first and second etch steps and the underlying substrate is etched during the third etch step. In the first etch step a carbon-fluorine based etchant is used in order to form a polymer layer along the photoresist, polish stop layer (or etch hard mask layer), and oxide layer. After the first etch step, a second etch step is used to remove the polymer from the horizontal surfaces of the semiconductor structures thereby forming polymer sidewalls as well as completing the etching of the polish stop layer (or etch hard mask layer) and the oxide layer. Polymer sidewalls protect the photoresist, polish stop layer (or etch hard mask layer), and oxide layer during the third etch step thereby improving the etch selectivity and etch bias control. The third etch step completes the formation of the trench by etching the substrate.

US Patent:

6001699, Dec 14, 1999

Filed:

Jan 23, 1996

Appl. No.:

8/589903

Inventors:

Phi L. Nguyen - Hillsboro OR
Mark A. Fradkin - Portland OR
Gilroy J. Vandentop - Aloha OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

C03C 1500

US Classification:

438305

Abstract:

A method for forming contacts with vertical sidewalls, high aspect ratios, improved salicide and photoresist etch selectivity at submicron dimensions. In one currently preferred embodiment, an opening is formed in a dual oxide layer by etching the undoped oxide layer at a first rate and then etching the doped oxide layer at a second rate. The etch process is performed in a low density parallel plate reactor. The process parameters of the etch are fixed in ranges which optimize the etch process and allow greater control over the critical dimensions of the opening. For example, the oxide layer is etched at a pressure in the range of approximately 100-300 mTorr and with an etch chemistry having a CHF. sub. 3 :CF. sub. 4 gas flow ratio in the range of approximately 3:1-1:1, respectively.