Phillip G Jones

US Patent:

7225560, Jun 5, 2007

Filed:

Feb 4, 2005

Appl. No.:

11/051277

Inventors:

Jeffrey P. Govek - Dallas TX, US
Steven M. Person - Seagoville TX, US
David M. Pizzillo - Carrollton TX, US
Phillip E. Jones - Carrollton TX, US
John E. Aylor - Fort Worth TX, US
David D. Douglas - Garland TX, US

Assignee:

Printing Research, Inc. - Dallas TX

International Classification:

F26B 3/34

US Classification:

34268, 34269

Abstract:

A system for curing printing plates with controlled radiant energy sources. A conveyor moves a printing plate through a chamber having energy radiators above and below the conveyor. Power to the radiators is controlled for each radiator or to groups of radiators defining radiation zones. Curing time may be controlled by adjusting power to the radiators and adjusting the conveyor speed. Sensors detect a plate as it enters and exits the chamber. Heat sensors may detect chamber or plate temperatures. A color sensor may detect plate color as an indicator of degree of curing. A computer system stores curing scenarios and uses the sensor signals and operator inputs to control power to the radiators and conveyor speed to provide uniform curing of the plate.

US Patent:

7685411, Mar 23, 2010

Filed:

Apr 11, 2005

Appl. No.:

11/104115

Inventors:

Muhammad Ahmed - Austin TX, US
Lucian Codrescu - Austin TX, US
Erich Plondke - Austin TX, US
William C. Anderson - Austin TX, US
Robert Allan Lester - Round Rock TX, US
Phillip M. Jones - Round Rock TX, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G06F 9/00

US Classification:

712241, 712239

Abstract:

An instruction memory unit comprises a first memory structure operable to store program instructions, and a second memory structure operable to store program instructions fetched from the first memory structure, and to issue stored program instructions for execution. The second memory structure is operable to identify a repeated issuance of a forward program redirect construct, and issue a next program instruction already stored in the second memory structure if a resolution of the forward branching instruction is identical to a last resolution of the same. The second memory structure is further operable to issue a backward program redirect construct, determine whether a target instruction is stored in the second memory structure, issue the target instruction if the target instruction is stored in the second memory structure, and fetch the target instruction from the first memory structure if the target instruction is not stored in the second memory structure.

US Patent:

7827356, Nov 2, 2010

Filed:

Sep 10, 2007

Appl. No.:

11/852348

Inventors:

Suresh Venkumahanti - Austin TX, US
Phillip Matthew Jones - Round Rock TX, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G06F 12/00

US Classification:

711128, 711125, 711156, 711159, 711202, 711221

Abstract:

A system and method of using an n-way cache are disclosed. In an embodiment, a method includes determining a first way of a first instruction stored in a cache and storing the first way in a list of ways. The method also includes determining a second way of a second instruction stored in the cache and storing the second way in the list of ways. In an embodiment, the first way may be used to access a first cache line containing the first instruction and the second way may be used to access a second cache line containing the second instruction.

US Patent:

20120117327, May 10, 2012

Filed:

Nov 8, 2010

Appl. No.:

12/941105

Inventors:

Suresh K. Venkumahanti - Austin TX, US
Lucian Codrescu - Austin TX, US
Stephen R. Shannon - Austin TX, US
Lin Wang - Austin TX, US
Phillip M. Jones - Austin TX, US
Daisy T. Palal - Las Vegas NV, US
Jiajin Tu - Austin TX, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

G06F 12/08

US Classification:

711125, 711E12016

Abstract:

Each branch instruction having branch prediction support has branch prediction bits in architecture specified bit positions in the branch instruction. An instruction cache supports modifying the branch instructions with updated branch prediction bits that are dynamically determined when the branch instruction executes.

US Patent:

20140181459, Jun 26, 2014

Filed:

Dec 20, 2012

Appl. No.:

13/721442

Inventors:

- San Diego CA, US
Jiajin Tu - Austin TX, US
Phillip M. Jones - Georgetown TX, US

Assignee:

QUAL COMM Incorporated - San Diego CA

International Classification:

G06F 12/10

US Classification:

711207

Abstract:

A method includes receiving an instruction to be executed by a processor. The method further includes performing a lookup in a page crossing buffer that includes one or more entries to determine if the instruction has an entry in the page crossing buffer. Each of the entries includes a physical address. The method further includes, when the page crossing buffer has the entry in the page crossing buffer, retrieving a particular physical address from the entry in the page crossing buffer.