Phillip R Krueger

US Patent:

6505286, Jan 7, 2003

Filed:

Sep 22, 2000

Appl. No.:

09/668948

Inventors:

Brent A. Kingsbury - Beaverton OR
Corene Casper - Beaverton OR
Phillip E. Krueger - Lake Oswego OR
Paul E. McKenney - Beaverton OR

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1202

US Classification:

711170, 711153, 711171, 711172, 711173

Abstract:

A method for a user process to specify a policy for allocating pages of physical memory on the nodes of a multinode multiprocessor computer system. Through means such as a system call, an application program can specify to the operating system that physical pages of memory for an application-specified portion of virtual address space are to be physically allocated upon a specified set of nodes, subject to the additional selection criteria that the pages are to be allocated at first reference upon: 1) the node upon which the reference first occurs; 2) the node which has the most free memory, or 3) that the pages should be evenly distributed across the indicated set of nodes. In effect, the operating system remembers the specified allocation policy and node set from which the physical pages can be subsequently allocated as established by a system call. Subsequent use of the virtual address space for which the allocation policy is defined results in the memory being allocated accordingly. In this way, an application program can use memory with the memory-locality most advantageous to it.

US Patent:

6615316, Sep 2, 2003

Filed:

Nov 16, 2000

Appl. No.:

09/715444

Inventors:

Paul E. McKenney - Beaverton OR
Phillip E. Krueger - Lake Oswego OR

Assignee:

International Business Machines, Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711118, 709102

Abstract:

A method and computer system for estimating cache warmth for thread schedulers in a processor of a multiprocessor system. A mathematical model based upon a Markov Model of queuing theory is used to determine flow probability. The method incorporates data received from cache counters to measure cache hits, cache misses, cache invalidations and cache roll-outs. Based upon the Model and the data received from the counters and the assumption that cache decays exponentially, a nominal lifetime of a cache line is computed and the state of the system is manipulated in accordance with the computed lifetime of the cache line. The method may be applied to either a two way LRU cache or a four way LRU cache for computing an average lifetime of a cache line. Accordingly, cache affinity and thread migration decisions are enhanced thereby providing an efficient method of operating a computer system.

US Patent:

6785888, Aug 31, 2004

Filed:

Feb 24, 1998

Appl. No.:

09/028285

Inventors:

Paul E. McKenney - Beaverton OR
Phillip E. Krueger - Lake Oswego OR
Stuart A. Friedberg - Aloha OR
Brent A. Kingsbury - Beaverton OR

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 900

US Classification:

718104, 709226, 709229, 710243, 711147

Abstract:

Methods for dynamically allocating memory in a multiprocessor computer system such as a non-uniform memory access (NUMA) machine having distributed shared memory. The methods include allocating memory by specified node, memory class, or memory pool in response to requests by the system (kernel memory allocation) or a user (application memory allocation). Through these methods memory is allocated more efficiently in a NUMA machine. For example, allocating memory on a specified node in a NUMA machine, such as the same node on which a process requiring the memory is running, reduces memory access time. Allocating memory from a specified memory class allows device drivers with restricted DMA ranges to operate with dynamically allocated memory. Other benefits of these methods include minimizing expensive remote-memory accesses using a distributed reference count mechanism and lock-free cache access.

US Patent:

7149853, Dec 12, 2006

Filed:

Sep 20, 2002

Appl. No.:

10/251689

Inventors:

Phillip E. Krueger - Lake Oswego OR, US

Assignee:

PolyServe, Inc. - Beaverton OR

International Classification:

G06F 12/00

US Classification:

711150, 711151, 711168

Abstract:

A system and method are disclosed for providing a synchronization mechanism for access to shared information. According to an embodiment of the present invention, a lock with more than one part can be obtained or leased by writing to the first part, writing to the second part, reading the first part to determine whether the first part reads what was written to it, and obtaining the lock if what is read is the same as what was written.

US Patent:

7472233, Dec 30, 2008

Filed:

Apr 30, 2004

Appl. No.:

10/835768

Inventors:

Paul E. McKenney - Beaverton OR, US
Phillip E. Krueger - Lake Oswego OR, US
Stuart A. Friedberg - Aloha OR, US
Brent A. Kingsbury - Beaverton OR, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711147, 711148, 711153, 711170, 711171

Abstract:

Methods for dynamically allocating memory in a multiprocessor computer system such as a non-uniform memory access (NUMA) machine having distributed shared memory. The methods include allocating memory by specified node, memory class, or memory pool in response to requests by the system (kernel memory allocation) or a user (application memory allocation). Through these methods memory is allocated more efficiently in a NUMA machine. For example, allocating memory on a specified node in a NUMA machine, such as the same node on which a process requiring the memory is running, reduces memory access time. Allocating memory from a specified memory class allows device drivers with restricted DMA ranges to operate with dynamically allocated memory. Other benefits of these methods include minimizing expensive remote-memory accesses using a distributed reference count mechanism and lock-free cache access.

US Patent:

20140047062, Feb 13, 2014

Filed:

Aug 7, 2012

Appl. No.:

13/568795

Inventors:

Phillip E. Krueger - Portland OR, US
Christopher August Shaffer - Portland OR, US

Assignee:

DELL PRODUCTS L.P. - Round Rock TX

International Classification:

G06F 15/167

US Classification:

709216

Abstract:

In one embodiment, a computing system includes a cache including one or more memories and a cache manager. The cache manager is able to determine an amount of accessible data for a portion of the cache associated with the cache manager; compare the amount of accessible data to a threshold value; determine, for one or more clients associated with the cache manager, an amount of releasable data if the amount of accessible data exceeds the threshold value; communicate, to one or more clients associated with the cache manager, the amount of releasable data for the client; receive from one or more clients associated with the cache manager information associated with data released by the one or more clients; and determine an amount of data released by the one or more clients associated with the cache manager.

US Patent:

20140047181, Feb 13, 2014

Filed:

Aug 7, 2012

Appl. No.:

13/568564

Inventors:

Scott David Peterson - Beaverton OR, US
Christopher August Shaffer - Portland OR, US
Phillip E. Krueger - Portland OR, US

Assignee:

DELL PRODUCTS L.P. - Round Rock TX

International Classification:

G06F 12/08

US Classification:

711118, 711E12017

Abstract:

In one embodiment, a computing system includes a cache having one or more memories and a cache manager. The cache manager is able to receive a request to write data to a first portion of the cache, write the data to the first portion of the cache, update a first map corresponding to the first portion of the cache, receive a request to read data from the first portion of the cache, read from a storage communicatively linked to the computing system data according to the first map, and update a second map corresponding to the first portion of the cache. The cache manager may also be able to write data to the storage according to the first map.

US Patent:

20140047185, Feb 13, 2014

Filed:

Aug 7, 2012

Appl. No.:

13/568850

Inventors:

Scott David Peterson - Beaverton OR, US
Phillip E. Krueger - Portland OR, US

Assignee:

DELL PRODUCTS L.P. - Round Rock TX

International Classification:

G06F 12/08

US Classification:

711123, 711E12024

Abstract:

In one embodiment, a computing system includes a cache and a cache manager. The cache manager is able to receive data, write the data to a first portion of the cache, write the data to a second portion of the cache, and delete the data from the second portion of the cache when the data in the first portion of the cache is flushed.