Pierre P Leroux

US Patent:

6465322, Oct 15, 2002

Filed:

Jan 15, 1998

Appl. No.:

09/007673

Inventors:

David Ziger - San Antonio TX
Edward Denison - Helotes TX
Pierre Leroux - San Antonio TX

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

H01L 2176

US Classification:

438401, 438 14, 438975, 148DIG 102

Abstract:

Methods and structures for determining alignment during semiconductor wafer processing are described. In one implementation, two geometric shapes are formed at different elevations over a substrate and at least partially overlapping with one another. The two shapes are inspected for overlap to determine whether the two shapes are misaligned. If the shapes are misaligned, a magnitude of misalignment is determined from the degree of overlap of the two shapes. In another implementation, a pair of elevationally spaced-apart geometric shapes are used to translate shifts of the shapes in one direction into quantifiable shift magnitudes using another direction. In yet another implementation, shifts in both the X and Y direction are readily quantifiable through visual inspection.

US Patent:

6541283, Apr 1, 2003

Filed:

Oct 21, 1999

Appl. No.:

09/422914

Inventors:

Pierre Leroux - San Antonio TX

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

H01L 2166

US Classification:

438 7, 430311

Abstract:

A method for determining magnification error portion of total misalignment error in a stepper. In one embodiment, the method comprises a series of steps in a stepper, starting with the step of receiving a wafer, having a first pattern and an error-free fine alignment target, in the stepper. In another step, the wafer is aligned in the stepper using the error-free fine alignment target. Then a second pattern is created on the wafer overlaying said first pattern. In another step, the magnification error portion of the total misalignment error is determined by measuring the radial misalignment between the first pattern and the second pattern.

US Patent:

6544859, Apr 8, 2003

Filed:

Nov 1, 2001

Appl. No.:

10/003130

Inventors:

David Ziger - San Antonio TX
Edward Dension - Helotes TX
Pierre Leroux - San Antonio TX

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

H01L 2176

US Classification:

438401, 438 14, 438975

Abstract:

Methods and structures for determining alignment during semiconductor wafer processing are described. In one implementation, two geometric shapes are formed at different elevations over a substrate and at least partially overlapping with one another. The two shapes are inspected for overlap to determine whether the two shapes are misaligned. If the shapes are misaligned, a magnitude of misalignment is determined from the degree of overlap of the two shapes. In another implementation, a pair of elevationally spaced-apart geometric shapes are used to translate shifts of the shapes in one direction into quantifiable shift magnitudes using another direction. In yet another implementation, shifts in both the X and Y direction are readily quantifiable through visual inspection.

US Patent:

6639676, Oct 28, 2003

Filed:

Oct 21, 1999

Appl. No.:

09/422909

Inventors:

Pierre Leroux - San Antonio TX

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

G01B 1100

US Classification:

356401

Abstract:

A method for determining rotational error portion of total misalignment error in a stepper. In one embodiment, the method comprises a series of steps in a stepper, starting with the step of receiving a wafer, having a first pattern and an error-free fine alignment target, in the stepper. In another step, the wafer is aligned in the stepper using the error-free fine alignment target. Then a second pattern is created on the wafer overlaying said first pattern. In another step, the rotational error portion of the total misalignment error is determined by measuring the circumferential misalignment between the first pattern and the second pattern.

US Patent:

6671048, Dec 30, 2003

Filed:

Oct 21, 1999

Appl. No.:

09/425834

Inventors:

Pierre Leroux - San Antonio TX

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

G01B 1100

US Classification:

356401

Abstract:

A method for determining wafer misalignment by using a pattern on a fine alignment target. In one embodiment, the method comprises a series of steps in a stepper, starting with the step of receiving a wafer having an alignment target. In another step, the wafer is aligned using the alignment target. Next, a pattern is created around the alignment target using an overlay. Then, the misalignment is determined between the alignment target and the pattern created around the alignment target.

US Patent:

6800403, Oct 5, 2004

Filed:

Jun 18, 2002

Appl. No.:

10/175367

Inventors:

Pierre Leroux - San Antonio TX
David Ziger - San Antonio TX

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

G03F 900

US Classification:

430 5, 430 30

Abstract:

A technique is provided to define a pattern ( ) on a substrate ( ) that includes a dense region with a number of features ( ) and an isolated feature region comprised of at least a part of one of the features ( ). The dense feature region has a greater feature density than the isolated feature region. A reference feature ( ) is measured at a number of different points relative to the isolated feature region and the dense feature region with a measurement tool ( ). An iso-dense effect is determined from these measurements.

US Patent:

6889162, May 3, 2005

Filed:

Mar 7, 2000

Appl. No.:

09/520686

Inventors:

Bryan Hubbard - Garland TX, US
Pierre Leroux - San Antonio TX, US

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

G01B011/00

US Classification:

702155, 702159, 356625

Abstract:

A method for determining the centroid of a wafer target. In one embodiment, the method comprises a series of steps in a stepper, starting with the step of receiving a wafer, having a target set formed therein. Next, a signal is passed over the target set and over a material separating target shapes in the target set. Then a return signal is reflected, and received, from the surface of the target shapes and the material separating them. A location of at least one maxima point of the return signal is identified. Finally, a centroid is determined as the median of the locations of at least one maxima point.

US Patent:

6950187, Sep 27, 2005

Filed:

Aug 29, 2003

Appl. No.:

10/652228

Inventors:

Pierre Leroux - San Antonio TX, US

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

G01B011/00

US Classification:

356400, 356401

Abstract:

A method for determining rotational error portion of total misalignment error in a stepper. In one embodiment, the method comprises a series of steps in a stepper, starting with the step of receiving a wafer, having a first pattern and an error-free fine alignment target, in the stepper. In another step, the wafer is aligned in the stepper using the error-free fine alignment target. Then a second pattern is created on the wafer overlaying said first pattern. In another step, the rotational error portion of the total misalignment error is determined by measuring the circumferential misalignment between the first pattern and the second pattern.