Pierre M Maillard

US Patent:

20200066713, Feb 27, 2020

Filed:

Aug 23, 2018

Appl. No.:

16/110894

Inventors:

- San Jose CA, US
James Karp - Saratoga CA, US
Mohammed Fakhruddin - San Jose CA, US
Pierre Maillard - Campbell CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H01L 27/06
H01L 27/02
H01L 29/73
H01L 29/78
H01L 49/02

Abstract:

Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a circuit includes a semiconductor substrate, a first transistor, a second transistor, and a ballast resistor. The semiconductor substrate comprises a p-doped region and an n-doped region. The first transistor comprises an n+ doped source region disposed in the p-doped region of the semiconductor substrate. The second transistor comprises a p+ doped source region disposed in the n-doped region of the semiconductor substrate. The p+ doped source region, the n-doped region, the p-doped region, and the n+ doped source region form a PNPN structure. The ballast resistor is electrically connected in series with the PNPN structure between a power node and a ground node.

US Patent:

20170287919, Oct 5, 2017

Filed:

Mar 31, 2016

Appl. No.:

15/087947

Inventors:

- San Jose CA, US
Pierre Maillard - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H01L 27/11
H01L 29/08
H01L 29/78

Abstract:

Front end circuits that include a FinFET transistor are described herein. In one example, the front end circuit has a FinFET transistor that includes a channel region wrapped by a metal gate, the channel region connecting a source and drain fins. At least one of the source and drain fins have a height (H) and a width W. The height (H) is greater than an optimal height (H), wherein the height His a height that would optimize speed of a FinFET transistor having the width W.