Pietro C Montanini

US Patent:

RE41856, Oct 26, 2010

Filed:

Aug 26, 2002

Appl. No.:

10/229396

Inventors:

Paolo Ferrari - Gallarate, IT
Benedetto Vigna - Potenza, IT
Pietro Montanini - Hopewell Junction NY, US
Marco Ferrera - Domodossola, IT

Assignee:

STMicroelectronics S.r.l. - Agrate (Brianza)

International Classification:

G01P 15/125
G01P 9/04

US Classification:

7351432, 7350412

Abstract:

A movable mass forming a seismic mass is formed starting from an epitaxial layer and is covered by a weighting region of tungsten which has high density. To manufacture the mass, buried conductive regions are formed in the substrate. Then, at the same time, a sacrificial region is formed in the zone where the movable mass is to be formed and oxide insulating regions are formed on the buried conductive regions so as to partially cover them. An epitaxial layer is then grown, using a nucleus region. A tungsten layer is deposited and defined and, using a silicon carbide layer as mask, the suspended structure is defined. Finally, the sacrificial region is removed, forming an air gap.

US Patent:

RE41889, Oct 26, 2010

Filed:

Feb 5, 2003

Appl. No.:

10/360367

Inventors:

Paolo Ferrari - Gallarate, IT
Benedetto Vigna - Potenza, IT
Pietro Montanini - Phoenix AZ, US
Marco Ferrera - Domodossola, IT

Assignee:

STMicroelectronics S.r.l. - Agrate (Brianza)

International Classification:

H01L 21/00

US Classification:

438 48, 438 52, 438 53, 257414, 257E21613

Abstract:

A movable mass forming a seismic mass is formed starting from an epitaxial layer and is covered by a weighting region of tungsten which has high density. To manufacture the mass, buried conductive regions are formed in the substrate. Then, at the same time, a sacrificial region is formed in the zone where the movable mass is to be formed and oxide insulating regions are formed on the buried conductive regions so as to partially cover them. An epitaxial layer is then grown, using a nucleus region. A tungsten layer is deposited and defined and, using a silicon carbide layer as mask, the suspended structure is defined. Finally, the sacrificial region is removed, forming an air gap.

US Patent:

8183098, May 22, 2012

Filed:

Nov 2, 2009

Appl. No.:

12/610463

Inventors:

Pietro Montanini - Phoenix AZ, US
Giuseppe Ammendola - S. Giuseppe Vesuviano, IT
Riccardo Depetro - Via Romita, IT
Marta Mottura - Phoenix AZ, US

Assignee:

STMicroelectronics S.r.l. - Agrate Brianza

International Classification:

H01L 21/762

US Classification:

438149, 438479, 438517, 257347, 257E21345, 257E21538, 257E21703

Abstract:

A method for manufacturing an integrated electronic device. The method includes providing an SOI substrate having a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor starting layer on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer on the insulating layer for integrating components of the device, and forming at least one contact trench extending from an exposed surface of the starting layer to the semiconductor substrate before the step of epitaxially growing the starting layer, wherein each contact trench clears a corresponding portion of the starting layer, of the insulating layer and of the semiconductor substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling the at least one contact trench with semiconductor material.

US Patent:

20220367626, Nov 17, 2022

Filed:

Jul 11, 2022

Appl. No.:

17/861960

Inventors:

- Armonk NY, US
Veeraraghavan S. Basker - Fremont CA, US
Andrew M. Greene - Slingerlands NY, US
Pietro Montanini - Albany NY, US

International Classification:

H01L 29/06
H01L 21/02
H01L 29/78
H01L 29/66

Abstract:

A method of forming a nanosheet transistor device is provided. The method includes forming a segment stack of alternating intermediate sacrificial segments and nanosheet segments on a bottom sacrificial segment, wherein the segment stack is on a mesa and a nanosheet template in on the segment stack. The method further includes removing the bottom sacrificial layer to form a conduit, and forming a fill layer in the conduit and encapsulating at least a portion of the segment stack.

US Patent:

20230099985, Mar 30, 2023

Filed:

Sep 24, 2021

Appl. No.:

17/484839

Inventors:

- Armonk NY, US
Oleg Gluschenkov - Tannersville NY, US
Andrew M. Greene - Slingerlands NY, US
Pietro Montanini - Albany NY, US

International Classification:

H01L 29/417
H01L 29/06
H01L 29/423
H01L 29/786
H01L 29/66

Abstract:

A semiconductor structure comprises a substrate defining a first axis and a second axis in orthogonal relation to the first axis, first and second nanosheet stacks disposed on the substrate, a gate structure on each of the first and second nanosheet stacks, a source/drain region adjacent each of the first and second nanosheet stacks, a wrap-around contact disposed about each source/drain region and an isolator pillar disposed between the wrap-around contacts.

US Patent:

20230075966, Mar 9, 2023

Filed:

Sep 7, 2021

Appl. No.:

17/468001

Inventors:

- Armonk NY, US
Chen Zhang - Guilderland NY, US
Jingyun Zhang - Albany NY, US
Junli Wang - Slingerlands NY, US
Pietro Montanini - Albany NY, US

International Classification:

H01L 29/78
H01L 29/06
H01L 29/08
H01L 29/417
H01L 29/66

Abstract:

A stacked transistor device is provided. The stacked transistor device includes a nanosheet transistor device on a substrate; and a fin field effect transistor device over the nanosheet transistor device to form the stacked transistor device, wherein the fin field effect transistor device is configured to have a current flow through the fin field effect transistor device perpendicular to a current flow through the nanosheet transistor device.

US Patent:

20210336035, Oct 28, 2021

Filed:

Apr 25, 2020

Appl. No.:

16/858598

Inventors:

- Armonk NY, US
Pietro Montanini - Guilderland NY, US

International Classification:

H01L 29/66
H01L 29/16
H01L 29/78

Abstract:

VTFET devices with bottom source and drain extensions are provided. In one aspect, a method of forming a VTFET device includes: patterning vertical fin channels in a substrate; forming sidewall spacers along the vertical fin channels having a liner and a spacer layer; forming recesses at a base of the vertical fin channels; indenting the liner; annealing the substrate under conditions sufficient to reshape the recesses; forming bottom source and drains in the recesses; forming bottom source and drain extensions in the substrate adjacent to the bottom source and drains; removing the sidewall spacers; forming bottom spacers on the bottom source and drains; forming gate stacks over the bottom spacers alongside the vertical fin channels; forming top spacers over the gate stacks; and forming top source and drains at tops of the vertical fin channels. A VTFET device by the method having bottom source and drain extensions is also provided.

US Patent:

20210151583, May 20, 2021

Filed:

Dec 28, 2020

Appl. No.:

17/135313

Inventors:

- Armonk NY, US
Ruilong Xie - Niskayuna NY, US
Pietro MONTANINI - ALBANY NY, US
Hemanth JAGANNATHAN - Niskayuna NY, US

International Classification:

H01L 29/66
H01L 29/78
H01L 21/02
H01L 21/28
H01L 21/285
H01L 21/311
H01L 21/8238
H01L 27/092
H01L 29/45
H01L 29/49

Abstract:

A semiconductor device structure and a method for fabricating the semiconductor device structure are disclosed. The method includes receiving a substrate stack including at least one semiconductor fin, the substrate stack including: a bottom source/drain epi region directly below the semiconductor fin; a vertical gate structure directly above the bottom source/drain epi region and in contact with the semiconductor fin; a first inter-layer dielectric in contact with a sidewall of the vertical gate structure; and a second interlayer-layer dielectric directly above and contacting a top surface of the first inter-layer dielectric. The method further including: etching a top region of the semiconductor fin and the gate structure thereby creating a recess directly above the top region of the semiconductor fin and the vertical gate structure; and forming in the recess a top source/drain epi region directly above, and contacting, a top surface of the semiconductor fin.