Ping K Chen

age ~83

from Fremont, CA

Also known as:
  • Pk K Chen
  • Helen Y Chen
  • Peggy Chen
Phone and address:
45907 Paseo Padre Pkwy, Fremont, CA 94539
5102708186

Ping Chen Phones & Addresses

  • 45907 Paseo Padre Pkwy, Fremont, CA 94539 • 5102708186
  • 39800 Fremont Blvd #175, Fremont, CA 94538
  • Fort Worth, TX
  • 33 Cienega, Irvine, CA 92618
  • 1833 Las Ramblas Dr, Concord, CA 94521
  • 180 Howard St, San Francisco, CA 94105
  • Orange, CA

Us Patents

  • Direct Access Logic Testing In Integrated Circuits

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  • US Patent:
    6385748, May 7, 2002
  • Filed:
    Mar 30, 1999
  • Appl. No.:
    09/281370
  • Inventors:
    Ping Chen - San Jose CA
  • Assignee:
    NEC Electronics, Inc. - Santa Clara CA
  • International Classification:
    G01R 3128
  • US Classification:
    714724, 365201
  • Abstract:
    A method and circuit for allowing direct access logic testing in integrated circuits. In one embodiment, an interface between integrated circuit core logic and integrated circuit user-defined logic is exposed, and the integrated circuit core logic and the integrated circuit user-defined logic is tested via the exposed interface. In another embodiment, an integrated circuit has logic selection circuitry connected with core logic and user-defined logic. The logic selection circuitry is used to selectively test the core logic and user-defined logic.
  • Method And System For Multiple Gpu Support

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  • US Patent:
    7325086, Jan 29, 2008
  • Filed:
    Dec 15, 2005
  • Appl. No.:
    11/300980
  • Inventors:
    Roy (Dehai) Kong - Cupertino CA, US
    Wen-Chung Chen - Cupertino CA, US
    Ping Chen - San Jose CA, US
    Irene (Chih-Yiieh) Cheng - San Jose CA, US
    Tatsang Mak - Milpitas CA, US
    Xi Liu - Shanghai, CN
    Li Zhang - ShangHai, CN
    Li Sun - Shanghai, CN
    Chenggang Liu - Shanghai, CN
  • Assignee:
    Via Technologies, Inc. - Hsin-Tien, Taipei
  • International Classification:
    G06F 13/40
  • US Classification:
    710307, 345503
  • Abstract:
    Supporting multiple graphics processing units (GPUs) comprises a first path coupled to a north bridge device (or a root complex device) and a first GPU, which may include a portion of the first GPU's total communication lanes. A second communication path may be coupled to the north bridge device and a second GPU and may include a portion of the second GPU's total communication lanes. A third communication path may be coupled between the first and second GPUs directly or through one or more switches that can be configured for single or multiple GPU operations. The third communication path may include some or all of the remaining communication lanes for the first and second GPUs. As a nonlimiting example, the first and second GPUs may each utilize an 8-lane PCI express communication path with the north bridge device and an 8-lane PCI express communication path with each other.
  • Switching Method And System For Multiple Gpu Support

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  • US Patent:
    7340557, Mar 4, 2008
  • Filed:
    Dec 15, 2005
  • Appl. No.:
    11/300705
  • Inventors:
    Dehai Kong - Cupertino CA, US
    Wen-Chung Chen - Cupertino CA, US
    Ping Chen - San Jose CA, US
    Irene Chih-Yiieh Cheng - San Jose CA, US
    Tatsang Mak - Milpitas CA, US
    Xi Liu - Shanghai, CN
    Li Zhang - ShangHai, CN
    Li Sun - Shanghai, CN
    Chenggang Liu - Shanghai, CN
  • Assignee:
    Via Technologies, Inc. - Taipei
  • International Classification:
    G06F 13/00
    G06F 13/36
  • US Classification:
    710316, 710306, 710311
  • Abstract:
    A system and method for supporting multiple graphics processing units (GPUs) includes a first communication path coupled to a root complex device and a first connection point of a first GPU. A second communication path is coupled to the root complex device and a first set of switches. The first set of switches is configured to route communications between the root complex device to either a second connection point of the first GPU via a second set of switches or to a first connection point of a second GPU. The second set of switches is coupled to a second connection point of the first GPU. The second set of switches is configured to route communications to and from the second connection point of the first GPU and to either the root complex device via the first set of switches or to a second connection point of the second GPU.
  • Hot-Carrier Device Degradation Modeling And Extraction Methodologies

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  • US Patent:
    7567891, Jul 28, 2009
  • Filed:
    Sep 27, 2001
  • Appl. No.:
    09/969185
  • Inventors:
    Zhihong Liu - Cupertino CA, US
    Lifeng Wu - Fremont CA, US
    Jeong Y. Choi - Palo Alto CA, US
    Ping Chen - San Jose CA, US
    Alvin I. Chen - San Jose CA, US
    Gang Zhang - Campbell CA, US
  • Assignee:
    Cadence Design Systems, Inc. - San Jose CA
  • International Classification:
    G06F 7/60
    G06F 17/50
    G06F 9/45
    G01R 15/00
    G01R 27/28
    G01R 27/26
    H03K 19/20
    H03K 19/094
  • US Classification:
    703 13, 703 2, 703 14, 716 4, 716 5, 324678, 326117, 326120, 326124, 702 57, 702117
  • Abstract:
    The present invention is directed to a number of improvements in methods for hot-carrier device degradation modeling and extraction. Several improvements are presented for the improvement of building device degradation models, including allowing the user to select a device parameter used to build the device degradation model independent of the device parameter selected. The user can also select the functional relation between stress time and degradation level. To further improve accuracy, multiple acceleration parameters can be used to account for different regions of the degradation process. Analytical functions may be used to represent aged device model parameters, either directly or by fitting measured device parameters versus device age values, allowing devices with different age values to share the same device model. The concept of binning is extended to include device degradation. In addition to a binning based on device width and length, age is added.
  • Geometry Primitive Type Conversion In A Gpu Pipeline

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  • US Patent:
    7696993, Apr 13, 2010
  • Filed:
    Feb 8, 2007
  • Appl. No.:
    11/672692
  • Inventors:
    Boris Prokopenko - Milpitas CA, US
    Hsilin (Stephen) Huang - Milpitas CA, US
    Ping Chen - San Jose CA, US
  • Assignee:
    VIA Technologies, Inc. - Hsin-Tien, Taipei
  • International Classification:
    G06T 17/00
  • US Classification:
    345420, 345423, 345441
  • Abstract:
    An input stream of graphics primitives may be converted into to a predetermined output stream of graphics primitives by a processor in a graphics pipeline. The processor recognizes a predetermined sequence pattern in the input stream of graphics primitives to the processor. The processor determines whether the recognized sequence pattern can be converted into the one of the plurality of predetermined output streams of graphics primitives. If so, the processor identifies a number of vertices in the recognized sequence pattern and reorders the vertices into a predetermined output pattern. Thereafter, the processor outputs the predetermined output pattern corresponding to one or more graphics processing components.
  • Method And Apparatus For Modeling Devices Having Different Geometries

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  • US Patent:
    7263477, Aug 28, 2007
  • Filed:
    Jun 9, 2003
  • Appl. No.:
    10/457945
  • Inventors:
    Ping Chen - San Jose CA, US
    Zhihong Liu - Cupertino CA, US
  • Assignee:
    Cadence Design Systems, Inc. - San Jose CA
  • International Classification:
    G06F 17/50
  • US Classification:
    703 13, 703 14, 703 2, 703 15, 716 1, 716 4, 700 31
  • Abstract:
    The present invention includes a method for modeling devices having different geometries, in which a range of interest for device geometrical variations is divided into a plurality of subregions each corresponding to a subrange of device geometrical variations. The plurality of subregions include a first type of subregions and a second type of subregions. The first or second type of subregions include one or more subregions. A regional global model is generated for each of the first type of subregions and a binning model is generated for each of the second type of subregions. The regional global model for a subregion uses one set of model parameters to comprehend the subrange of device geometrical variations corresponding to the G-type subregion. The binning model for a subregion includes binning parameters to provide continuity of the model parameters when device geometry varies across two different subregions.
  • Extracting Semiconductor Device Model Parameters

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  • US Patent:
    20030220779, Nov 27, 2003
  • Filed:
    Mar 31, 2003
  • Appl. No.:
    10/404630
  • Inventors:
    Ping Chen - San Jose CA, US
    Jushan Xie - Campbell CA, US
  • International Classification:
    G06F017/50
    G06F009/45
  • US Classification:
    703/014000, 703/022000
  • Abstract:
    The present invention includes a method for extracting semiconductor device model parameters for a device model such as the BSIMPD model. The method comprises obtaining terminal current data corresponding to various bias conditions in a set of test devices and extracting a portion of a plurality of DC model parameters for the device model from the terminal current data. The terminal current are then modified based on the extracted portion of the DC model parameters before extracting additional DC model parameters. The present invention also includes novel methods for extracting some of the DC model parameters.
  • Modeling Devices In Consideration Of Process Fluctuations

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  • US Patent:
    20040073879, Apr 15, 2004
  • Filed:
    May 15, 2003
  • Appl. No.:
    10/439755
  • Inventors:
    Ping Chen - San Jose CA, US
    Xisheng Zhang - Sunnyvale CA, US
  • International Classification:
    G06F017/50
  • US Classification:
    716/008000, 716/004000, 703/002000, 703/014000
  • Abstract:
    The present invention includes a method for generating typical and corner device models to account for statistical variations in a semiconductor device fabrication process. The typical and corner models can be generated before the semiconductor device fabrication process is fully developed based on a process specification associated with the semiconductor device fabrication process. The typical and corner models can also be generated with better accuracy after the semiconductor device fabrication process is developed and measured data are available for model generation.

Real Estate Brokers

Ping Chen Photo 1

Ping Chen, Alhambra CA Real Estate Agent

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Specialties:
Buyer's Agent
Listing Agent
Work:
Coldwell Banker George Realty
1611 S. Garfield Ave, Alhambra, CA 91754
6263780611 (Office), 6263780611 (Cell), 6265290923 (Fax)
Experience:
15 years
Description:
Specializing in South Pasadena homes for sale and the Los Angeles County real estate market, you have found your realtor resource for buying and selling your next San Marino home or Arcadia house. With expertiese in realty for both purchasing and lsing properties in South Pasadena, San Marino, Arcadia, Alhambra, San Gabriel and Monterey Park and all surrounding Los Angeles County, CA areas, you have found the right resource for all of your real estate needs. With about ten years senior sales experience, I take great pride in helping people achieve the dream of home ownership. I do so with intergrity and exceptional service! Whether you are looking for a new Alhambra property or San Marino land, or you are in the preliminary stages of a South Pasadena real estate search, you have found the best in professional service. Personal I was born in Henan province in China and graduated from Henan University with a major in music. After graduation, I moved to GuangDong. Consequently, I'm fluent in Mandarin and Cantonese and would be pleased to assist you in meeting your real estate needs.
Links:
Site
Blog
Facebook
Twitter
LinkedIn
Ping Chen Photo 2

Ping Chen, Diamond Bar CA Agent

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Work:
Century 21
Diamond Bar, CA
9098612800 (Phone)
Name / Title
Company / Classification
Phones & Addresses
Ping Chen
Owner
Hunan Star
Restaurants
8116 Olive Blvd, St Louis, MO 63130-2023
Ping Chen
Director of Platform Software
Data Domain, Inc.
2300 Central Expy, Santa Clara, CA 95050
Ping Chen
Owner
Golden State Marble & Granite
Cut Stone and Stone Products
114 S Amphlett Blvd, San Mateo, CA 94401
Website: goldenstatemarble.com
Ping Chen
Manager
Angelitas Restaurant
Eating Places
1190 Hillsdale Ave Ste 148, San Jose, CA 95118
Ping Chen
President
EPIC AQUATICS INC
Business Services at Non-Commercial Site · Nonclassifiable Establishments
6834 Andaravida Rd, Corona, CA 92880
Ping Chen
Owner
Golden State Marble & Granite, Inc
Marble & Granite Installation · Stonework Fabrication · Stone Cutters
114 S Amphlett Blvd, San Mateo, CA 94401
6503423318, 6503423218
Ping Chang Chen
President
PIONEER MATERIAL PRECISION TECH, INC
Business Services at Non-Commercial Site · Business Services, Nec, Nsk
1301 Sunnyvale-Saratoga Rd, Sunnyvale, CA 94085
20863 Stevens Crk Blvd, Cupertino, CA 95014
1301 Sunnyvale Saratoga Rd, Sunnyvale, CA 94087
6454 Windsor Ln, San Jose, CA 95129
Ping Chen
President
Green Health Outlet, Inc
Miscellaneous Retail Stores, Nec, Nsk · Ret Misc Merchandise
9040 Telstar Ave, El Monte, CA 91731
8930 Msn Dr, Rosemead, CA 91770
6262869898

License Records

Ping Chen

License #:
4704224720 - Expired
Category:
Nursing
Issued Date:
May 11, 2000
Expiration Date:
Mar 31, 2003
Type:
RN

Ping K Chen

Address:
45907 Paseo Padre Pkwy, Fremont, CA 94539
License #:
28171 - Expired
Issued Date:
Mar 23, 1992
Renew Date:
Apr 1, 2004
Expiration Date:
Mar 31, 2006
Type:
Professional Engineer

Resumes

Ping Chen Photo 3

Ping Chen Pomona, CA

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Work:
85C Bakery Cafe
Brea, CA
Feb 2014 to Oct 2014
Production Management
Unified We Serve
Los Angeles, CA
Sep 2012 to Mar 2013
Volunteer
Display Taiwan Exhibition

Jun 2011 to Aug 2011
Interpreter
Chuang-Lian Insurance Broker Co., Ltd

Jul 2008 to Jul 2009
Assistant
Eden Social Welfare Foundation

Jun 2007 to Jul 2007
International Volunteer
Education:
California State University
Aug 2010 to May 2014
Bachelor of Science in Finance
Ming Chuan University
Sep 2008 to Dec 2009
Bachelor of Science in Risk Management & Insurance
Skills:
Languages: English, Mandarin Computer: Microsoft Word, Power Point, Excel
Ping Chen Photo 4

Ping Chen Fremont, CA

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Work:
Castlight Health

Apr 2014 to 2000
Program Manager
Johnson & Johnson (J&J)
US and ASPAC
Apr 2014 to Jun 2014
Senior Manager
Johnson and Johnson - LifeScan Diabetes Franchise, Medical Devices Sector
Milpitas, CA
Sep 2012 to Apr 2014
Senior Manager, Digital IT
Johnson and Johnson - R&D, Commercial, Supply Chain, Asia Pacific Pharmaceutical Sector

Sep 2010 to Sep 2012
Account Manager
Johnson and Johnson - Global Project Management, Corporate Offices
Milpitas, CA
Jun 2008 to Sep 2010
Project Manager
Johnson & Johnson Information Management Leadership Development Program
US Domestic
Jun 2006 to Jun 2008
Leadership Development Program
Hua Yuan Science and Technology Association (HYSTA)
Silicon Valley, CA
Volunteer
Education:
University of California, Berkeley
Berkeley, CA
2002 to 2006
Bachelor of Arts in Cognitive Science emphasis in Neuroscience
Skills:
Native fluency in Mandarin.

Medicine Doctors

Ping Chen Photo 5

Ping Chen

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Specialties:
Physical Medicine & Rehabilitation
Work:
Southeastern Integrated MedicalSoutheast Integrated Medical Rehabilitation Medicine
1315 NW 21 Ave STE 2, Chiefland, FL 32626
3524931655 (phone), 3524908641 (fax)
Languages:
English
Description:
Ms. Chen works in Chiefland, FL and specializes in Physical Medicine & Rehabilitation. Ms. Chen is affiliated with UF Health Shands Rehabilitation Hospital.

Youtube

Being Anti-America Is Work , Living In Americ...

"Being anti-America is work, living in America is life". This phrase h...

  • Duration:
    13m 13s

Chen Ping - Three Prospects of China-US Trade...

Chen Ping, he described the current situation of China-US trade war. *...

  • Duration:
    7m 22s

Land of Big Numbers with Te-Ping Chen and Cha...

Join the Asian American Writers' Workshop for the official launch of T...

  • Duration:
    1h 9m 49s

Ping Chen Interview

Dr. Ping Chen, PhD, is a research grant recipient from Regenerative Me...

  • Duration:
    2m 12s

(Full Audiobook) Land of Big Numbers by Te Pi...

(Full Audiobook) Land of Big Numbers by Te Ping Chen - Great Novel A d...

  • Duration:
    6h 37m 22s

Te-Ping Chen, in conversation with Jiayang Fa...

(2/09/21) Gripping and compassionate, Land of Big Numbers traces the j...

  • Duration:
    54m 29s

Googleplus

Ping Chen Photo 6

Ping Chen

Work:
Google, Inc - Software Engineer (2006)
America Online
Education:
University of California, Irvine
Relationship:
Married
About:
I love building cool stuff, but I love taking photos even more :) Other hobbies include food and travel  Disclaimer: The views expressed by me are mine (all mine!) and not my employer's.
Bragging Rights:
Climbed down 71 flights of stairs in Taipei 101 building
Ping Chen Photo 7

Ping Chen

Ping Chen Photo 8

Ping Chen

Education:
Camberwell College of Arts
Ping Chen Photo 9

Ping Chen

Ping Chen Photo 10

Ping Chen

About:
陈平, 画家
Bragging Rights:
艺术家
Ping Chen Photo 11

Ping Chen (Yaway Watan)

Ping Chen Photo 12

Ping Chen

Ping Chen Photo 13

Ping Chen

Plaxo

Ping Chen Photo 14

Ping Chen

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RBC Mortgage
Ping Chen Photo 15

chen ping

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TCBIO

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