Pinhong Chen

US Patent:

7082587, Jul 25, 2006

Filed:

Dec 18, 2002

Appl. No.:

10/323399

Inventors:

Pinhong Chen - Fremont CA, US
Chin-Chi Teng - Sunnyvale CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 6, 716 4

Abstract:

To estimate path delays within an IC, a serial database is first created to hold and read out RC extraction data for nets within the IC in an order in which the RC extraction data will be needed when estimating path delays. Thereafter, as the RC extraction data is sequentially read out of the database for each net, the path delay though each section of the net is computed and added to the estimated path delay for each signal path including that net section. The RC extraction data for each net is accessed and accessed only once, thereby minimizing the processing time needed to perform timing analysis by minimizing hard disk read accesses when the RC extraction database resides on a hard disk.

US Patent:

7551985, Jun 23, 2009

Filed:

Oct 30, 2006

Appl. No.:

11/590068

Inventors:

Pinhong Chen - Saratoga CA, US
Wilsin Gosti - Fremont CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 19/00

US Classification:

700297, 700286

Abstract:

Method and apparatus for finding an assignment of voltages to all power domains of an integrated circuit such that the power consumption of an integrated circuit design is minimized and timing requirements (signal propagation delay or slack) are met. This is done by modeling both internal and external signal paths in an integrated circuit which has a number of power domains. The relationship between slack and voltage for the external and internal signal propagation paths is modeled, typically as a linear approximation. The integrated circuit design is then abstracted to a simplified form in terms of power domain relations and a model is created and solved iteratively using, e. g. , linear programming, of different voltage levels for each power domain and including the slack values and their relationship between the changes in voltage and slack, for both the internal and external paths.

US Patent:

7739629, Jun 15, 2010

Filed:

Oct 30, 2006

Appl. No.:

11/590657

Inventors:

Qi Wang - San Jose CA, US
Ankur Gupta - Mountain View CA, US
Pinhong Chen - Saratoga CA, US
Christina Chu - San Jose CA, US
Manish Pandey - San Jose CA, US
Huan-Chih Tsai - Saratoga CA, US
Sandeep Bhatia - San Jose CA, US
Yonghao Chen - Groton MA, US
Steven Sharp - Lowell MA, US
Vivek Chickermane - Ithaca NY, US
Patrick Gallagher - Appalachian NY, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 4, 716 2, 716 7, 703 14

Abstract:

A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.

US Patent:

7954078, May 31, 2011

Filed:

Jun 29, 2007

Appl. No.:

11/771953

Inventors:

Qi Wang - San Jose CA, US
Pinhong Chen - Saratoga CA, US
Mitchell W. Hines - San Jose CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716127, 716106, 716109, 716111, 716120, 716133

Abstract:

A method to produce an information structure in computer readable memory that specifies power source hierarchy information for an RTL circuit design that includes multiple function instances encoded in computer readable memory, comprising: providing associations within the memory between respective function instances of the RTL design and respective power domains so as to define respective primary power domains relative to the RTL design; specifying in the memory respective secondary power domains; and providing associations within the memory that are indicative of respective power source relationships between respective primary power domains and corresponding respective secondary power domains.

US Patent:

8516422, Aug 20, 2013

Filed:

Jun 14, 2010

Appl. No.:

12/815239

Inventors:

Qi Wang - San Jose CA, US
Ankur Gupta - Mountain View CA, US
Pinhong Chen - Saratoga CA, US
Christina Chu - San Jose CA, US
Manish Pandey - San Jose CA, US
Huan-Chih Tsai - Saratoga CA, US
Sandeep Bhatia - San Jose CA, US
Yonghao Chen - Groton MA, US
Steven Sharp - Lowell MA, US
Vivek Chickermane - Ithaca NY, US
Patrick Gallagher - Appalachian NY, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716109, 716111, 716120, 716123, 716133, 716127, 716136, 703 16

Abstract:

A method for implementing a single file format for power-related information for an IC comprising: providing a circuit design in at least one design file in a non-transitory computer readable storage device; providing power-related design information in a file in the computer readable storage device that is separate from the at least one design file and that specifies multiple power domains within the circuit design, each power domain including one or more design object instances from within the circuit design and that specifies multiple power modes each power mode corresponding to a different combination of on/off states of the multiple specified power domains and that specifies isolation behavior relative to respective power domains; and using a computer to add power control circuitry to the circuit design that implements the power domains and power modes and isolation behavior specified in the power specification information.

US Patent:

RE44479, Sep 3, 2013

Filed:

Jun 12, 2012

Appl. No.:

13/494363

Inventors:

Qi Wang - San Jose CA, US
Ankur Gupta - Mountain View CA, US
Pinhong Chen - Saratoga CA, US
Christina Chu - San Jose CA, US
Manish Pandey - San Jose CA, US
Huan-Chih Tsai - Saratoga CA, US
Sandeep Bhatia - San Jose CA, US
Yonghoa Chen - Groton MA, US
Steven Sharp - Lowell MA, US
Vivek Chickermane - Ithaca NY, US
Patrick Gallagher - Appalachian NY, US
Mitchell W. Hines - San Jose CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716105, 716102, 716103, 703 14

Abstract:

A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.

US Patent:

20030115563, Jun 19, 2003

Filed:

Dec 5, 2002

Appl. No.:

10/313866

Inventors:

Pinhong Chen - Fremont CA, US

International Classification:

G06F017/50

US Classification:

716/005000, 716/012000, 716/007000, 716/004000

Abstract:

Crosstalk noise peaks in output signals of nets of an integrated circuit layout design are estimated by first processing the design to estimate resistances and capacitances of the nets. The design is then processed to identify each aggressor net having at least one section that is proximate to a section of a victim net. A separate aggressor model is then generated for each proximate aggressor net section, the aggressor model including a current source and a capacitor. The design is then processed to identify each victim net that is proximate any aggressor net and a separate crosstalk model is generated for each identified victim net. The crosstalk model for each victim net includes the victim net's estimated resistances and capacitances and incorporates the aggressor model of each aggressor net section that is proximate to a section of the identified victim net. The crosstalk model for each identified victim net is then evaluated to determine a response to a signal applied as input to the victim net of a victim net output signal. The peak crosstalk noise in each identified victim net is estimated based on the response of the net's output signal.