Piyush C Savalia

age ~45

from Salinas, CA

Also known as:
  • Ufus Savalia

Piyush Savalia Phones & Addresses

  • Salinas, CA
  • 6962 Calabazas Creek Cir, San Jose, CA 95129
  • Sunnyvale, CA
  • Santa Clara, CA
  • Auburn, AL

Work

  • Company:
    Private
    2018
  • Position:
    Consultant and founder

Education

  • Degree:
    Master of Science, Masters
  • School / High School:
    Auburn University
    2003 to 2006
  • Specialities:
    Mechanical Engineering

Skills

Electronics • Design of Experiments • Engineering • Manufacturing • Failure Analysis • Product Development • Finite Element Analysis • Characterization • Cross Functional Team Leadership • Electronics Packaging • Ic • Mems • Process Engineering • Testing • Mechanical Engineering • Optics • Sensors • R&D • Product Management • Program Management • Research and Development • Materials • Semiconductor Industry • Integrated Circuits • Intellectual Property • Mechanical Design • 3D Cad • Computer Aided Design • Consumer Products • Solidworks • Consumer Electronics • Finite Element Analysis

Languages

English • Mandarin • Hindi • Gujarati • German

Industries

Semiconductors

Us Patents

  • Electrohydrodynamic Fluid Accelerator Device With Collector Electrode Exhibiting Curved Leading Edge Profile

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  • US Patent:
    8466624, Jun 18, 2013
  • Filed:
    Sep 3, 2009
  • Appl. No.:
    12/553688
  • Inventors:
    Nels Jewell-Larsen - Campbell CA, US
    Kenneth A. Honer - Santa Clara CA, US
    Matt Schwiebert - Cupertino CA, US
    Hongyu Ran - Mountain View CA, US
    Piyush Savalia - San Jose CA, US
    Yan Zhang - San Jose CA, US
  • Assignee:
    Tessera, Inc. - San Jose CA
  • International Classification:
    H05B 31/26
  • US Classification:
    31511191, 315500, 315506
  • Abstract:
    Performance of an electrohydrodynamic fluid accelerator device may be improved and adverse events such as sparking or arcing may be reduced based, amongst other things, on electrode geometries and/or positional interrelationships of the electrodes. For example, in a class of EHD devices that employ a longitudinally elongated corona discharge electrode (often, but not necessarily, a wire), a plurality of generally planar, collector electrodes may be positioned so as to present respective leading surfaces toward the corona discharge electrode. The generally planar collector electrodes may be oriented so that their major surfaces are generally orthogonal to the longitudinal extent of the corona discharge electrode. In such EHD devices, a high intensity electric field can be established in the “gap” between the corona discharge electrode and leading surfaces of the collector electrodes.
  • Simultaneous Wafer Bonding And Interconnect Joining

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  • US Patent:
    8486758, Jul 16, 2013
  • Filed:
    Mar 31, 2011
  • Appl. No.:
    13/076969
  • Inventors:
    Vage Oganesian - Palo Alto CA, US
    Belgacem Haba - Saratoga CA, US
    Ilyas Mohammed - Santa Clara CA, US
    Piyush Savalia - Santa Clara CA, US
    Craig Mitchell - San Jose CA, US
  • Assignee:
    Tessera, Inc. - San Jose CA
  • International Classification:
    H01L 21/00
    H01L 23/48
  • US Classification:
    438107, 438455, 257777, 257E21087, 257E21088, 257E21499
  • Abstract:
    Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.
  • Dual Wafer Spin Coating

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  • US Patent:
    8512491, Aug 20, 2013
  • Filed:
    Dec 21, 2010
  • Appl. No.:
    12/974611
  • Inventors:
    Vage Oganesian - Palo Alto CA, US
    Belgacem Haba - Saratoga CA, US
    Ilyas Mohammed - Santa Clara CA, US
    Piyush Savalia - Santa Clara CA, US
    Craig Mitchell - San Jose CA, US
  • Assignee:
    Tessera, Inc. - San Jose CA
  • International Classification:
    B32B 41/00
  • US Classification:
    156 64, 156350, 156351, 156358, 156360, 156361, 156367, 156378, 156379, 156 74, 156 87, 156 88
  • Abstract:
    A method of bonding a first substrate and a second substrate includes the steps of rotating first substrate with an adhesive mass thereon, and second substrate contacting the mass and overlying the first substrate, controlling a vertical height of a heated control platen spaced apart from and not contacting the second substrate so as to control a temperature of the adhesive mass, so as to at least one of bond the first and second substrates in alignment with one another, or achieve a sufficiently planar adhesive interface between the first and second substrates.
  • Stacked Microelectronic Assembly With Tsvs Formed In Stages With Plural Active Chips

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  • US Patent:
    8587126, Nov 19, 2013
  • Filed:
    Mar 18, 2011
  • Appl. No.:
    13/051414
  • Inventors:
    Vage Oganesian - Sunnyvale CA, US
    Belgacem Haba - Saratoga CA, US
    Ilyas Mohammed - Santa Clara CA, US
    Craig Mitchell - San Jose CA, US
    Piyush Savalia - Santa Clara CA, US
  • Assignee:
    Tessera, Inc. - San Jose CA
  • International Classification:
    H01L 23/48
    H01L 23/52
  • US Classification:
    257774, 257686, 257777, 257E23145
  • Abstract:
    A microelectronic assembly is provided in which first and second electrically conductive pads exposed at front surfaces of first and second microelectronic elements, respectively, are juxtaposed, each of the microelectronic elements embodying active semiconductor devices. An electrically conductive element may extend within a first opening extending from a rear surface of the first microelectronic element towards the front surface thereof, within a second opening extending from the first opening towards the front surface of the first microelectronic element, and within a third opening extending through at least one of the first and second pads to contact the first and second pads. Interior surfaces of the first and second openings may extend in first and second directions relative to the front surface of the first microelectronic element, respectively, to define a substantial angle.
  • Active Chip On Carrier Or Laminated Chip Having Microelectronic Element Embedded Therein

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  • US Patent:
    8598695, Dec 3, 2013
  • Filed:
    Jul 23, 2010
  • Appl. No.:
    12/842692
  • Inventors:
    Vage Oganesian - Palo Alto CA, US
    Ilyas Mohammed - Santa Clara CA, US
    Craig Mitchell - San Jose CA, US
    Belgacem Haba - Saratoga CA, US
    Piyush Savalia - San Jose CA, US
  • Assignee:
    Tessera, Inc. - San Jose CA
  • International Classification:
    H01L 23/02
  • US Classification:
    257686, 257723, 257773, 257777, 257E23141, 257E25013, 438109
  • Abstract:
    A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to connect the additional microelectronic element to the active elements of the first chip. The structure may have a volume comparable to that of the first chip alone and yet provide the functionality of a multi-chip assembly. A composite chip incorporating a body and a layer of semiconductor material mounted on a front surface of the body similarly may have a cavity extending into the body from the rear surface and may have an additional microelectronic element mounted in such cavity.
  • Multi-Function And Shielded 3D Interconnects

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  • US Patent:
    8610259, Dec 17, 2013
  • Filed:
    Sep 17, 2010
  • Appl. No.:
    12/884695
  • Inventors:
    Vage Oganesian - Palo Alto CA, US
    Belgacem Haba - Saratoga CA, US
    Ilyas Mohammed - Santa Clara CA, US
    Craig Mitchell - San Jose CA, US
    Piyush Savalia - Santa Clara CA, US
  • Assignee:
    Tessera, Inc. - San Jose CA
  • International Classification:
    H01L 23/48
  • US Classification:
    257692, 257E21597, 438667
  • Abstract:
    A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element.
  • Compliant Interconnects In Wafers

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  • US Patent:
    8610264, Dec 17, 2013
  • Filed:
    Dec 8, 2010
  • Appl. No.:
    12/962806
  • Inventors:
    Vage Oganesian - Palo Alto CA, US
    Belgacem Haba - Saratoga CA, US
    Ilyas Mohammed - Santa Clara CA, US
    Piyush Savalia - Santa Clara CA, US
    Craig Mitchell - San Jose CA, US
  • Assignee:
    Tessera, Inc. - San Jose CA
  • International Classification:
    H01L 23/488
    H01L 21/60
  • US Classification:
    257724, 257779, 257E23015, 257E23067, 257E25013, 438109, 438612
  • Abstract:
    A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/ C. , a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit.
  • Stacked Microelectronic Assembly Having Interposer Connecting Active Chips

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  • US Patent:
    8637968, Jan 28, 2014
  • Filed:
    Dec 2, 2010
  • Appl. No.:
    12/958866
  • Inventors:
    Belgacem Haba - Saratoga CA, US
    Vage Oganesian - Palo Alto CA, US
    Ilyas Mohammed - Santa Clara CA, US
    Piyush Savalia - Santa Clara CA, US
    Craig Mitchell - San Jose CA, US
  • Assignee:
    Tessera, Inc. - San Jose CA
  • International Classification:
    H01L 23/48
    H01L 23/02
    H01L 29/40
  • US Classification:
    257686, 257276, 257777
  • Abstract:
    A microelectronic assembly can include first and second microelectronic elements each embodying active semiconductor devices adjacent a front surface thereof, and having an electrically conductive pad exposed at the respective front surface. An interposer of material having a CTE less than 10 ppm/ C. has first and second surfaces attached to the front surfaces of the respective first and second microelectronic elements, the interposer having a second conductive element extending within an opening in the interposer. First and second conductive elements extend within openings extending from the rear surface of a respective microelectronic element of the first and second microelectronic elements towards the front surface of the respective microelectronic element. In one example, one or more of the first or second conductive elements extends through the respective first or second pad, and the conductive elements contact the exposed portions of the second conductive element to provide electrical connection therewith.

Resumes

Piyush Savalia Photo 1

Consultant And Founder

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Private
Consultant and Founder

Insilixa Dec 2015 - Feb 2017
Senior Manager, Mechanical Engineering

Jawbone Feb 2013 - Dec 2015
Senior Manager, Mechanical Engineering and Systems Reliability

Intersil Aug 2012 - Jan 2013
Staff Packaging Engineer, Ww Operations

Intersil Sep 2011 - Aug 2012
Lead Packaging Engineer, Ww Operations
Education:
Auburn University 2003 - 2006
Master of Science, Masters, Mechanical Engineering
Sardar Patel University, Vallabh Vidyanagar 1998 - 2002
Bachelors, Bachelor of Science, Mechanical Engineering
Skills:
Electronics
Design of Experiments
Engineering
Manufacturing
Failure Analysis
Product Development
Finite Element Analysis
Characterization
Cross Functional Team Leadership
Electronics Packaging
Ic
Mems
Process Engineering
Testing
Mechanical Engineering
Optics
Sensors
R&D
Product Management
Program Management
Research and Development
Materials
Semiconductor Industry
Integrated Circuits
Intellectual Property
Mechanical Design
3D Cad
Computer Aided Design
Consumer Products
Solidworks
Consumer Electronics
Finite Element Analysis
Languages:
English
Mandarin
Hindi
Gujarati
German

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