Pradipta K Ghosh

US Patent:

6694495, Feb 17, 2004

Filed:

Jun 12, 2001

Appl. No.:

09/879506

Inventors:

Hunaid Hussain - Milpitas CA
Pradipta Ghosh - Milpitas CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1750

US Classification:

716 4, 716 2, 716 18, 714724

Abstract:

A method is provided for analyzing a test vector for use in measuring static current consumed by an integrated circuit that has an embedded memory device. According to the method, a potential test vector is applied to a functional model of the integrated circuit. The logic states of various nodes in the integrated circuit are detected in response to the potential test vector. At least some of the nodes correspond to the input address bits of the memory device, where the memory device has a valid address range on the input address bits. An output is produced for the potential test vector based on whether these logic states correspond to an address within the valid address range.

US Patent:

6449751, Sep 10, 2002

Filed:

Jun 12, 2001

Appl. No.:

09/879417

Inventors:

Hunaid Hussain - Milpitas CA
Pradipta Ghosh - Milpitas CA
Arun K. Gunda - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1750

US Classification:

716 4, 716 12, 716 18

Abstract:

A method and apparatus are provided for analyzing test vectors for use in measuring static current consumed by an integrated circuit. A netlist of interconnected cells is read to identify cell types used within the netlist, wherein the netlist includes a plurality of nodes. Once the netlist has been read, cell characteristics for selected ones of the cell types are read from a technology library to identify pins of the selected cell types to be monitored. The nodes in the netlist that correspond to these pins are identified and are added to an list file. Once the list file has been generated, a computer simulation program is used to simulate a steady-state response of a functional model of the integrated circuit to a potential test vector and to output the resulting logic states on the nodes provided in the list file.