Qi I Wu

US Patent:

20220188225, Jun 16, 2022

Filed:

Dec 14, 2020

Appl. No.:

17/120386

Inventors:

- San Jose CA, US
Qi Wu - San Jose CA, US

International Classification:

G06F 12/06
G06F 7/08
G06F 3/06
G06F 11/07

Abstract:

An infrastructure for mapping between logic block addresses (LBAs) and physical block addresses (PBAs). A disclosed method includes: receiving a request the specifies an LBA; determining an applicable zone based on the LBA from a set of zones, wherein the set of zones expose an LBA address space of the storage device; identifying at least one tree from a set of trees having a root node associated with the applicable zone; traversing the at least one tree to identify a set of leaf nodes based on the LBA, wherein each leaf node points to an mpage; and determining corresponding PBA information for the LBA by examining mapping information contained in each mpage.

US Patent:

20200034234, Jan 30, 2020

Filed:

Jul 25, 2019

Appl. No.:

16/521703

Inventors:

- San Jose CA, US
Qi Wu - San Jose CA, US

International Classification:

G06F 11/10
G06F 12/10

Abstract:

A method for implementing a RAID group in a system including a host computing system, a first set of storage devices for storing user data for the RAID group, and a second set of storage devices for storing redundancy data for the RAID group. The method includes: distributing the user data from a host-side FLT module on the host computing system to the first set of storage devices; determining, by each storage device in the first set of storage devices, a logical block address to physical block address (LBA-PBA) binding for the user data received from the host-side FLT module; sending LBA-PBA binding information for the LBA-PBA binding from the first set of storage devices to the host-side FLT module; and performing, by the host-side FLT module, RAID encoding to form the RAID group based on the LBA-PBA binding information received from the first set of storage devices.

US Patent:

20200034286, Jan 30, 2020

Filed:

Jul 25, 2019

Appl. No.:

16/521711

Inventors:

- San Jose CA, US
Qi Wu - San Jose CA, US

International Classification:

G06F 12/02
G06F 3/06
G06F 12/0802
G06F 12/1009

Abstract:

The present disclosure relates to the field of solid-state data storage, and particularly to improving the write throughput performance of solid-state data storage devices. A method for providing logical block address (LBA) to physical block address (PBA) binding in a storage device includes: receiving at least one thread at a hardware engine of the device controller of the storage device, each thread including data and LBAs for the data; writing the data into a write buffer of the storage device; binding, by the hardware engine of the device controller, a sequence of contiguous PBAs for a section of the memory to the LBAs for the data in the write buffer; determining if the write buffer contains enough data for the section of the memory; and if the write buffer contains enough data for the section of the memory, writing the data to the section of the memory.

US Patent:

20190056870, Feb 21, 2019

Filed:

Aug 15, 2018

Appl. No.:

15/998430

Inventors:

- San Jose CA, US
Jinjin He - Santa Clara CA, US
Qi Wu - San Jose CA, US

International Classification:

G06F 3/06

Abstract:

A storage device, infrastructure, and associated method for managing request queue to reduce read tail latencies. A disclosed storage device is disclosed that includes: a set of flash memory chips; and a controller that schedules request from a host using a set of request queues, wherein the controller includes a queue manager that: reorders high priority read requests over low priority write requests in each request queue; suspends low priority write requests to process high priority read requests; and limits a number of low priority write requests allowed in each request queue to a threshold value smaller than a size of each request queue.

US Patent:

20170344303, Nov 30, 2017

Filed:

Mar 14, 2017

Appl. No.:

15/458945

Inventors:

- San Jose CA, US
Ladislav STEFFKO - San Ramon CA, US
Qi WU - San Jose CA, US

International Classification:

G06F 3/06
G06F 12/1027
G06F 17/30
G06F 12/10
G06F 12/1018
G06F 12/02

Abstract:

A translation system can translate a request having multiple fields to a physical address using the fields as indexes to a multi-dimensional graph. A field or portion of a field can represent a location along an axis. When combined together, the fields can represent a point in n-space, where n is the number of axes. In some embodiments, a nearest neighbor calculation can be sufficient along an axis. Therefore, a point in n-space defined by the fields can be translated along an axis until a nearest neighbor entry is determined. When the entry is determined, the entry can be accessed to determine a correct response to the translation request.

US Patent:

20170199826, Jul 13, 2017

Filed:

Mar 27, 2017

Appl. No.:

15/470695

Inventors:

- San Jose CA, US
Ladislav STEFFKO - San Ramon CA, US
Qi WU - San Jose CA, US

International Classification:

G06F 12/1018
G06F 17/30
G06F 12/02
G06F 12/1027
G06F 3/06

Abstract:

A translation system can translate a storage request to a physical address using fields as keys to traverse a map of nodes with node entries. A node entry can include a link to a next node or a physical address. Using a portion of the key as noted in node metadata, a node entry can be determined. When adding node entries to a node, a node utilization can exceed a threshold value. A new node can be created such that node entries are split between the original and new node. Node metadata of the parent node, new node and original node can be revised to identify which parts of the key are used to identify a node entry. When removing node entries from a node, node utilization can cross a minimum threshold value. Node entries from the node can be merged with a sibling, or the map can be rebalanced.

US Patent:

20160147474, May 26, 2016

Filed:

Feb 1, 2016

Appl. No.:

15/012260

Inventors:

- San Jose CA, US
Qi WU - San Jose CA, US

International Classification:

G06F 3/06

Abstract:

A memory system including parent data and clone data is disclosed, where the clone data represents a clone of the parent data. The system determines whether clone data to be accessed is different from corresponding data in the parent. The system also determines a physical location of the data to be accessed based on whether the data to be accessed is different from the corresponding parent data. The system also accesses the data based on the physical location.

US Patent:

20160147475, May 26, 2016

Filed:

Feb 1, 2016

Appl. No.:

15/012294

Inventors:

- San Jose CA, US
Qi WU - San Jose CA, US

International Classification:

G06F 3/06

Abstract:

A memory system including parent data and clone data is disclosed, where the clone data represents a clone of the parent data. The system determines whether clone data to be accessed is different from corresponding data in the parent. The system also determines a physical location of the data to be accessed based on whether the data to be accessed is different from the corresponding parent data. The system also accesses the data based on the physical location.